| Message ID | 1565984527-5272-13-git-send-email-skomatineni@nvidia.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | SC7 entry and exit support for Tegra210 | expand |
On Fri, Aug 16, 2019 at 12:41:57PM -0700, Sowjanya Komatineni wrote: > This patch adds suspend and resume pm ops for cpufreq driver. > > PLLP is the safe clock source for CPU during system suspend and > resume as PLLP rate is below the CPU Fmax at Vmin. > > CPUFreq driver suspend switches the CPU clock source to PLLP and > disables the DFLL clock. > > During system resume, warmboot code powers up the CPU with PLLP > clock source. So CPUFreq driver resume enabled DFLL clock and > switches CPU back to DFLL clock source. > > Acked-by: Thierry Reding <treding@nvidia.com> > Acked-by: Viresh Kumar <viresh.kumar@linaro.org> > Reviewed-by: Dmitry Osipenko <digetx@gmail.com> > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> > --- > drivers/cpufreq/tegra124-cpufreq.c | 59 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 59 insertions(+) Hi Rafael, I was originally planning to pick this up into the Tegra tree with your and Viresh's Acked-by, but I now realize that there aren't any dependencies between this and the rest of the series, so this can also go through your tree. Do you have any preference on how to merge it? I've already Acked this from the Tegra side, so feel free to pick it up if that's what you prefer. Thierry > diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c > index 4f0c637b3b49..7a1ea6fdcab6 100644 > --- a/drivers/cpufreq/tegra124-cpufreq.c > +++ b/drivers/cpufreq/tegra124-cpufreq.c > @@ -6,6 +6,7 @@ > #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt > > #include <linux/clk.h> > +#include <linux/cpufreq.h> > #include <linux/err.h> > #include <linux/init.h> > #include <linux/kernel.h> > @@ -128,8 +129,66 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) > return ret; > } > > +static int __maybe_unused tegra124_cpufreq_suspend(struct device *dev) > +{ > + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev); > + int err; > + > + /* > + * PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to > + * use during suspend and resume. So, switch the CPU clock source > + * to PLLP and disable DFLL. > + */ > + err = clk_set_parent(priv->cpu_clk, priv->pllp_clk); > + if (err < 0) { > + dev_err(dev, "failed to reparent to PLLP: %d\n", err); > + return err; > + } > + > + clk_disable_unprepare(priv->dfll_clk); > + > + return 0; > +} > + > +static int __maybe_unused tegra124_cpufreq_resume(struct device *dev) > +{ > + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev); > + int err; > + > + /* > + * Warmboot code powers up the CPU with PLLP clock source. > + * Enable DFLL clock and switch CPU clock source back to DFLL. > + */ > + err = clk_prepare_enable(priv->dfll_clk); > + if (err < 0) { > + dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err); > + goto disable_cpufreq; > + } > + > + err = clk_set_parent(priv->cpu_clk, priv->dfll_clk); > + if (err < 0) { > + dev_err(dev, "failed to reparent to DFLL clock: %d\n", err); > + goto disable_dfll; > + } > + > + return 0; > + > +disable_dfll: > + clk_disable_unprepare(priv->dfll_clk); > +disable_cpufreq: > + disable_cpufreq(); > + > + return err; > +} > + > +static const struct dev_pm_ops tegra124_cpufreq_pm_ops = { > + SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend, > + tegra124_cpufreq_resume) > +}; > + > static struct platform_driver tegra124_cpufreq_platdrv = { > .driver.name = "cpufreq-tegra124", > + .driver.pm = &tegra124_cpufreq_pm_ops, > .probe = tegra124_cpufreq_probe, > }; > > -- > 2.7.4 >
diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c index 4f0c637b3b49..7a1ea6fdcab6 100644 --- a/drivers/cpufreq/tegra124-cpufreq.c +++ b/drivers/cpufreq/tegra124-cpufreq.c @@ -6,6 +6,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include <linux/clk.h> +#include <linux/cpufreq.h> #include <linux/err.h> #include <linux/init.h> #include <linux/kernel.h> @@ -128,8 +129,66 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) return ret; } +static int __maybe_unused tegra124_cpufreq_suspend(struct device *dev) +{ + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev); + int err; + + /* + * PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to + * use during suspend and resume. So, switch the CPU clock source + * to PLLP and disable DFLL. + */ + err = clk_set_parent(priv->cpu_clk, priv->pllp_clk); + if (err < 0) { + dev_err(dev, "failed to reparent to PLLP: %d\n", err); + return err; + } + + clk_disable_unprepare(priv->dfll_clk); + + return 0; +} + +static int __maybe_unused tegra124_cpufreq_resume(struct device *dev) +{ + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev); + int err; + + /* + * Warmboot code powers up the CPU with PLLP clock source. + * Enable DFLL clock and switch CPU clock source back to DFLL. + */ + err = clk_prepare_enable(priv->dfll_clk); + if (err < 0) { + dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err); + goto disable_cpufreq; + } + + err = clk_set_parent(priv->cpu_clk, priv->dfll_clk); + if (err < 0) { + dev_err(dev, "failed to reparent to DFLL clock: %d\n", err); + goto disable_dfll; + } + + return 0; + +disable_dfll: + clk_disable_unprepare(priv->dfll_clk); +disable_cpufreq: + disable_cpufreq(); + + return err; +} + +static const struct dev_pm_ops tegra124_cpufreq_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend, + tegra124_cpufreq_resume) +}; + static struct platform_driver tegra124_cpufreq_platdrv = { .driver.name = "cpufreq-tegra124", + .driver.pm = &tegra124_cpufreq_pm_ops, .probe = tegra124_cpufreq_probe, };