| Message ID | 20191106011723.2110-1-hch@lst.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [resend] riscv: move sifive_l2_cache.c to drivers/soc | expand |
On Tue, Nov 05, 2019 at 05:17:23PM -0800, Christoph Hellwig wrote: > The sifive_l2_cache.c is in no way related to RISC-V architecture > memory management. It is a little stub driver working around the fact > that the EDAC maintainers prefer their drivers to be structured in a > certain way that doesn't fit the SiFive SOCs. > > Move the file to drivers/soc and add a Kconfig option for it, as well > as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE. > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") > Signed-off-by: Christoph Hellwig <hch@lst.de> > --- > > I'll still need ACKs from the edac maintainers for this according to > Paul.. > > MAINTAINERS | 1 + > arch/riscv/mm/Makefile | 1 - > drivers/edac/Kconfig | 2 +- > drivers/soc/Kconfig | 1 + > drivers/soc/Makefile | 1 + > drivers/soc/sifive/Kconfig | 10 ++++++++++ > drivers/soc/sifive/Makefile | 4 ++++ > .../riscv/mm => drivers/soc/sifive}/sifive_l2_cache.c | 0 > 8 files changed, 18 insertions(+), 2 deletions(-) > create mode 100644 drivers/soc/sifive/Kconfig > create mode 100644 drivers/soc/sifive/Makefile > rename {arch/riscv/mm => drivers/soc/sifive}/sifive_l2_cache.c (100%) > > diff --git a/MAINTAINERS b/MAINTAINERS > index cba1095547fd..f5a8accb0df3 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -5972,6 +5972,7 @@ M: Yash Shah <yash.shah@sifive.com> > L: linux-edac@vger.kernel.org > S: Supported > F: drivers/edac/sifive_edac.c > +F: drivers/soc/sifive/ I'm assuming that file pattern will change once the riscv EDAC driver is converted to be per functional unit... > diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile > new file mode 100644 > index 000000000000..9b4a85558347 > --- /dev/null > +++ b/drivers/soc/sifive/Makefile > @@ -0,0 +1,4 @@ > +# SPDX-License-Identifier: GPL-2.0 > + > +obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o > + Fix that up before applying: .git/rebase-apply/patch:105: new blank line at EOF. + Also, building with a cross-compiler fails here: drivers/soc/sifive/sifive_l2_cache.c:178:1: warning: data definition has no type or storage class device_initcall(sifive_l2_init); ^~~~~~~~~~~~~~~ drivers/soc/sifive/sifive_l2_cache.c:178:1: error: type defaults to 'int' in declaration of 'device_initcall' [-Werror=implicit-int] drivers/soc/sifive/sifive_l2_cache.c:178:1: warning: parameter names (without types) in function declaration drivers/soc/sifive/sifive_l2_cache.c:145:19: warning: 'sifive_l2_init' defined but not used [-Wunused-function] static int __init sifive_l2_init(void) ^~~~~~~~~~~~~~ cc1: some warnings being treated as errors make[3]: *** [scripts/Makefile.build:266: drivers/soc/sifive/sifive_l2_cache.o] Error 1 make[2]: *** [scripts/Makefile.build:509: drivers/soc/sifive] Error 2 make[1]: *** [scripts/Makefile.build:509: drivers/soc] Error 2 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1649: drivers] Error 2 .config attached.
On Wed, Nov 06, 2019 at 10:10:13AM +0100, Borislav Petkov wrote:
> Also, building with a cross-compiler fails here:
What config? riscv defconfig + CONFIG_SIFIVE_L2 works just fine for me.
On Wed, Nov 06, 2019 at 03:48:59PM +0100, Christoph Hellwig wrote: > On Wed, Nov 06, 2019 at 10:10:13AM +0100, Borislav Petkov wrote: > > Also, building with a cross-compiler fails here: > > What config? riscv defconfig + CONFIG_SIFIVE_L2 works just fine for me. Do you not see the one I attached? I'm attaching it again. $ grep -E "(EDAC|SIFIVE_L2)" .config CONFIG_EDAC_SUPPORT=y CONFIG_EDAC=y # CONFIG_EDAC_LEGACY_SYSFS is not set # CONFIG_EDAC_DEBUG is not set CONFIG_EDAC_SIFIVE=y CONFIG_SIFIVE_L2=m $ make.cross ARCH=riscv make CROSS_COMPILE=/home/share/src/crosstool/gcc-8.1.0-nolibc/riscv64-linux/bin/riscv64-linux- --jobs=32 ARCH=riscv ... drivers/soc/sifive/sifive_l2_cache.c:178:1: warning: data definition has no type or storage class device_initcall(sifive_l2_init); ^~~~~~~~~~~~~~~ drivers/soc/sifive/sifive_l2_cache.c:178:1: error: type defaults to 'int' in declaration of 'device_initcall' [-Werror=implicit-int] drivers/soc/sifive/sifive_l2_cache.c:178:1: warning: parameter names (without types) in function declaration drivers/soc/sifive/sifive_l2_cache.c:145:19: warning: 'sifive_l2_init' defined but not used [-Wunused-function] static int __init sifive_l2_init(void) ^~~~~~~~~~~~~~ cc1: some warnings being treated as errors make[3]: *** [scripts/Makefile.build:266: drivers/soc/sifive/sifive_l2_cache.o] Error 1 make[2]: *** [scripts/Makefile.build:509: drivers/soc/sifive] Error 2 make[1]: *** [scripts/Makefile.build:509: drivers/soc] Error 2 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1649: drivers] Error 2
On Wed, Nov 06, 2019 at 04:02:59PM +0100, Borislav Petkov wrote: > On Wed, Nov 06, 2019 at 03:48:59PM +0100, Christoph Hellwig wrote: > > On Wed, Nov 06, 2019 at 10:10:13AM +0100, Borislav Petkov wrote: > > > Also, building with a cross-compiler fails here: > > > > What config? riscv defconfig + CONFIG_SIFIVE_L2 works just fine for me. > > Do you not see the one I attached? Sorry, missed it. The problem is that you have a modular build, which doesn't make much sense given that the actual EDAC_SIFIVE needs to be built-in anyway. I've changed it to bool and will resend.
diff --git a/MAINTAINERS b/MAINTAINERS index cba1095547fd..f5a8accb0df3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5972,6 +5972,7 @@ M: Yash Shah <yash.shah@sifive.com> L: linux-edac@vger.kernel.org S: Supported F: drivers/edac/sifive_edac.c +F: drivers/soc/sifive/ EDAC-SKYLAKE M: Tony Luck <tony.luck@intel.com> diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index 9d9a17335686..b225134c29e0 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -11,7 +11,6 @@ obj-y += extable.o obj-y += ioremap.o obj-y += cacheflush.o obj-y += context.o -obj-y += sifive_l2_cache.o ifeq ($(CONFIG_MMU),y) obj-$(CONFIG_SMP) += tlbflush.o diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 417dad635526..5c8272329a65 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -462,7 +462,7 @@ config EDAC_ALTERA_SDMMC config EDAC_SIFIVE bool "Sifive platform EDAC driver" - depends on EDAC=y && RISCV + depends on EDAC=y && SIFIVE_L2 help Support for error detection and correction on the SiFive SoCs. diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 833e04a7835c..1778f8c62861 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -14,6 +14,7 @@ source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" source "drivers/soc/rockchip/Kconfig" source "drivers/soc/samsung/Kconfig" +source "drivers/soc/sifive/Kconfig" source "drivers/soc/sunxi/Kconfig" source "drivers/soc/tegra/Kconfig" source "drivers/soc/ti/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 2ec355003524..8b49d782a1ab 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -20,6 +20,7 @@ obj-y += qcom/ obj-y += renesas/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_SOC_SAMSUNG) += samsung/ +obj-$(CONFIG_SOC_SIFIVE) += sifive/ obj-y += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig new file mode 100644 index 000000000000..9ffb2e8a48cd --- /dev/null +++ b/drivers/soc/sifive/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 + +if SOC_SIFIVE + +config SIFIVE_L2 + tristate "Sifive L2 Cache controller" + help + Support for the L2 cache controller on SiFive platforms. + +endif diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile new file mode 100644 index 000000000000..9b4a85558347 --- /dev/null +++ b/drivers/soc/sifive/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o + diff --git a/arch/riscv/mm/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c similarity index 100% rename from arch/riscv/mm/sifive_l2_cache.c rename to drivers/soc/sifive/sifive_l2_cache.c
The sifive_l2_cache.c is in no way related to RISC-V architecture memory management. It is a little stub driver working around the fact that the EDAC maintainers prefer their drivers to be structured in a certain way that doesn't fit the SiFive SOCs. Move the file to drivers/soc and add a Kconfig option for it, as well as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Christoph Hellwig <hch@lst.de> --- I'll still need ACKs from the edac maintainers for this according to Paul.. MAINTAINERS | 1 + arch/riscv/mm/Makefile | 1 - drivers/edac/Kconfig | 2 +- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/sifive/Kconfig | 10 ++++++++++ drivers/soc/sifive/Makefile | 4 ++++ .../riscv/mm => drivers/soc/sifive}/sifive_l2_cache.c | 0 8 files changed, 18 insertions(+), 2 deletions(-) create mode 100644 drivers/soc/sifive/Kconfig create mode 100644 drivers/soc/sifive/Makefile rename {arch/riscv/mm => drivers/soc/sifive}/sifive_l2_cache.c (100%)