| Message ID | 90a64d72a32dbc75c03a58a1813f50e547170ff4.1572950559.git.eswara.kota@linux.intel.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | PCI: Add Intel PCIe Driver and respective dt-binding yaml file | expand |
On Wed, Nov 6, 2019 at 3:44:3, Dilip Kota <eswara.kota@linux.intel.com> wrote: > Utilize DesugnWare helper functions to configure Fast Training > Sequence. Drop the respective code in the driver. Please fix s/DesugnWare/DesignWare > > Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> > --- > drivers/pci/controller/dwc/pcie-artpec6.c | 8 +------- > 1 file changed, 1 insertion(+), 7 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c > index d00252bd8fae..02d93b8c7942 100644 > --- a/drivers/pci/controller/dwc/pcie-artpec6.c > +++ b/drivers/pci/controller/dwc/pcie-artpec6.c > @@ -51,9 +51,6 @@ static const struct of_device_id artpec6_pcie_of_match[]; > #define ACK_N_FTS_MASK GENMASK(15, 8) > #define ACK_N_FTS(x) (((x) << 8) & ACK_N_FTS_MASK) > > -#define FAST_TRAINING_SEQ_MASK GENMASK(7, 0) > -#define FAST_TRAINING_SEQ(x) (((x) << 0) & FAST_TRAINING_SEQ_MASK) > - > /* ARTPEC-6 specific registers */ > #define PCIECFG 0x18 > #define PCIECFG_DBG_OEN BIT(24) > @@ -313,10 +310,7 @@ static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie) > * Set the Number of Fast Training Sequences that the core > * advertises as its N_FTS during Gen2 or Gen3 link training. > */ > - val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); > - val &= ~FAST_TRAINING_SEQ_MASK; > - val |= FAST_TRAINING_SEQ(180); > - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); > + dw_pcie_link_set_n_fts(pci, 180); > } > > static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie) > -- > 2.11.0
On 11/5/19, 10:44 PM, Dilip Kota wrote: > > Utilize DesugnWare helper functions to configure Fast Training Nitpicking: Fix typo (DesugnWare --> DesignWare) If possible, how about the following? Utilize DesignWare --> Use DesignWare Best regards, Jingoo Han > Sequence. Drop the respective code in the driver. > > Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> > --- > drivers/pci/controller/dwc/pcie-artpec6.c | 8 +------- > 1 file changed, 1 insertion(+), 7 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c > index d00252bd8fae..02d93b8c7942 100644 > --- a/drivers/pci/controller/dwc/pcie-artpec6.c > +++ b/drivers/pci/controller/dwc/pcie-artpec6.c > @@ -51,9 +51,6 @@ static const struct of_device_id artpec6_pcie_of_match[]; > #define ACK_N_FTS_MASK GENMASK(15, 8) > #define ACK_N_FTS(x) (((x) << 8) & ACK_N_FTS_MASK) > > -#define FAST_TRAINING_SEQ_MASK GENMASK(7, 0) > -#define FAST_TRAINING_SEQ(x) (((x) << 0) & FAST_TRAINING_SEQ_MASK) > - > /* ARTPEC-6 specific registers */ > #define PCIECFG 0x18 > #define PCIECFG_DBG_OEN BIT(24) > @@ -313,10 +310,7 @@ static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie) > * Set the Number of Fast Training Sequences that the core > * advertises as its N_FTS during Gen2 or Gen3 link training. > */ > - val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); > - val &= ~FAST_TRAINING_SEQ_MASK; > - val |= FAST_TRAINING_SEQ(180); > - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); > + dw_pcie_link_set_n_fts(pci, 180); > } > > static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie) > -- > 2.11.0
On Thu, Nov 07, 2019 at 09:03:46PM +0000, Jingoo Han wrote: > On 11/5/19, 10:44 PM, Dilip Kota wrote: > > > > Utilize DesugnWare helper functions to configure Fast Training > > Nitpicking: Fix typo (DesugnWare --> DesignWare) > > If possible, how about the following? > Utilize DesignWare --> Use DesignWare > > Best regards, > Jingoo Han > > > Sequence. Drop the respective code in the driver. > > > > Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> With the changes suggested in this thread, you can add: Reviewed-by: Andrew Murray <andrew.murray@arm.com> > > --- > > drivers/pci/controller/dwc/pcie-artpec6.c | 8 +------- > > 1 file changed, 1 insertion(+), 7 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c > > index d00252bd8fae..02d93b8c7942 100644 > > --- a/drivers/pci/controller/dwc/pcie-artpec6.c > > +++ b/drivers/pci/controller/dwc/pcie-artpec6.c > > @@ -51,9 +51,6 @@ static const struct of_device_id artpec6_pcie_of_match[]; > > #define ACK_N_FTS_MASK GENMASK(15, 8) > > #define ACK_N_FTS(x) (((x) << 8) & ACK_N_FTS_MASK) > > > > -#define FAST_TRAINING_SEQ_MASK GENMASK(7, 0) > > -#define FAST_TRAINING_SEQ(x) (((x) << 0) & FAST_TRAINING_SEQ_MASK) > > - > > /* ARTPEC-6 specific registers */ > > #define PCIECFG 0x18 > > #define PCIECFG_DBG_OEN BIT(24) > > @@ -313,10 +310,7 @@ static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie) > > * Set the Number of Fast Training Sequences that the core > > * advertises as its N_FTS during Gen2 or Gen3 link training. > > */ > > - val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); > > - val &= ~FAST_TRAINING_SEQ_MASK; > > - val |= FAST_TRAINING_SEQ(180); > > - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); > > + dw_pcie_link_set_n_fts(pci, 180); > > } > > > > static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie) > > -- > > 2.11.0 >
On 11/6/2019 5:43 PM, Gustavo Pimentel wrote: > On Wed, Nov 6, 2019 at 3:44:3, Dilip Kota <eswara.kota@linux.intel.com> > wrote: > >> Utilize DesugnWare helper functions to configure Fast Training >> Sequence. Drop the respective code in the driver. > Please fix > s/DesugnWare/DesignWare Typo error. I will correct it in the next patch version. Thanks for reviewing it. Regards, Dilip
On 11/8/2019 5:03 AM, Jingoo Han wrote: > On 11/5/19, 10:44 PM, Dilip Kota wrote: >> Utilize DesugnWare helper functions to configure Fast Training > Nitpicking: Fix typo (DesugnWare --> DesignWare) > > If possible, how about the following? > Utilize DesignWare --> Use DesignWare Sure, i will correct it and update to 'Use DesignWare' Thanks for reviewing the patch, Regards, Dilip > > Best regards, > Jingoo Han >
On 11/8/2019 6:43 PM, Andrew Murray wrote: > On Thu, Nov 07, 2019 at 09:03:46PM +0000, Jingoo Han wrote: >> On 11/5/19, 10:44 PM, Dilip Kota wrote: >>> Utilize DesugnWare helper functions to configure Fast Training >> Nitpicking: Fix typo (DesugnWare --> DesignWare) >> >> If possible, how about the following? >> Utilize DesignWare --> Use DesignWare >> >> Best regards, >> Jingoo Han >> >>> Sequence. Drop the respective code in the driver. >>> >>> Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> > With the changes suggested in this thread, you can add: > > Reviewed-by: Andrew Murray <andrew.murray@arm.com> Sure. Thanks a lot for reviewing patch and giving inputs, Regards, Dilip > >>> --- >>> drivers/pci/controller/dwc/pcie-artpec6.c | 8 +------- >>> 1 file changed, 1 insertion(+), 7 deletions(-) >>> >>> diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c >>> index d00252bd8fae..02d93b8c7942 100644 >>> --- a/drivers/pci/controller/dwc/pcie-artpec6.c >>> +++ b/drivers/pci/controller/dwc/pcie-artpec6.c >>> @@ -51,9 +51,6 @@ static const struct of_device_id artpec6_pcie_of_match[]; >>> #define ACK_N_FTS_MASK GENMASK(15, 8) >>> #define ACK_N_FTS(x) (((x) << 8) & ACK_N_FTS_MASK) >>> >>> -#define FAST_TRAINING_SEQ_MASK GENMASK(7, 0) >>> -#define FAST_TRAINING_SEQ(x) (((x) << 0) & FAST_TRAINING_SEQ_MASK) >>> - >>> /* ARTPEC-6 specific registers */ >>> #define PCIECFG 0x18 >>> #define PCIECFG_DBG_OEN BIT(24) >>> @@ -313,10 +310,7 @@ static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie) >>> * Set the Number of Fast Training Sequences that the core >>> * advertises as its N_FTS during Gen2 or Gen3 link training. >>> */ >>> - val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); >>> - val &= ~FAST_TRAINING_SEQ_MASK; >>> - val |= FAST_TRAINING_SEQ(180); >>> - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); >>> + dw_pcie_link_set_n_fts(pci, 180); >>> } >>> >>> static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie) >>> -- >>> 2.11.0
diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index d00252bd8fae..02d93b8c7942 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -51,9 +51,6 @@ static const struct of_device_id artpec6_pcie_of_match[]; #define ACK_N_FTS_MASK GENMASK(15, 8) #define ACK_N_FTS(x) (((x) << 8) & ACK_N_FTS_MASK) -#define FAST_TRAINING_SEQ_MASK GENMASK(7, 0) -#define FAST_TRAINING_SEQ(x) (((x) << 0) & FAST_TRAINING_SEQ_MASK) - /* ARTPEC-6 specific registers */ #define PCIECFG 0x18 #define PCIECFG_DBG_OEN BIT(24) @@ -313,10 +310,7 @@ static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie) * Set the Number of Fast Training Sequences that the core * advertises as its N_FTS during Gen2 or Gen3 link training. */ - val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - val &= ~FAST_TRAINING_SEQ_MASK; - val |= FAST_TRAINING_SEQ(180); - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_link_set_n_fts(pci, 180); } static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
Utilize DesugnWare helper functions to configure Fast Training Sequence. Drop the respective code in the driver. Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> --- drivers/pci/controller/dwc/pcie-artpec6.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-)