| Message ID | 20191114083436.2261-1-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/selftests: Exercise rc6 handling | expand |
Quoting Chris Wilson (2019-11-14 08:34:36) > Reading from CTX_INFO upsets rc6, requiring us to detect and prevent > possible rc6 context corruption. Poke at the bear! > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_rc6.c | 4 + > drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 13 +++ > drivers/gpu/drm/i915/gt/selftest_rc6.c | 89 +++++++++++++++++++ > drivers/gpu/drm/i915/gt/selftest_rc6.h | 12 +++ > .../drm/i915/selftests/i915_live_selftests.h | 1 + > 5 files changed, 119 insertions(+) > create mode 100644 drivers/gpu/drm/i915/gt/selftest_rc6.c > create mode 100644 drivers/gpu/drm/i915/gt/selftest_rc6.h > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c > index f7c0baeb3793..0de35d18a2b2 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c > @@ -777,3 +777,7 @@ u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg) > { > return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000); > } > + > +#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) > +#include "selftest_rc6.c" > +#endif > diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c > index d1752f15702a..1d5bf93d1258 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c > +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c > @@ -6,6 +6,7 @@ > */ > > #include "selftest_llc.h" > +#include "selftest_rc6.h" > > static int live_gt_resume(void *arg) > { > @@ -58,3 +59,15 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915) > > return intel_gt_live_subtests(tests, &i915->gt); > } > + > +int intel_gt_pm_late_selftests(struct drm_i915_private *i915) > +{ > + static const struct i915_subtest tests[] = { > + SUBTEST(live_rc6_ctx), > + }; > + > + if (intel_gt_is_wedged(&i915->gt)) > + return 0; > + > + return intel_gt_live_subtests(tests, &i915->gt); > +} > diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c > new file mode 100644 > index 000000000000..9b02016c81a9 > --- /dev/null > +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c > @@ -0,0 +1,89 @@ > +/* > + * SPDX-License-Identifier: MIT > + * > + * Copyright © 2019 Intel Corporation > + */ > + > +#include "intel_context.h" > +#include "intel_engine_pm.h" > +#include "intel_gt_requests.h" > +#include "intel_ring.h" > +#include "selftest_rc6.h" > + > +static const u32 *__live_rc6_ctx(struct intel_context *ce) > +{ > + struct i915_request *rq; > + u32 const *result; > + u32 *cs; > + > + rq = intel_context_create_request(ce); > + if (IS_ERR(rq)) > + return ERR_CAST(rq); > + > + cs = intel_ring_begin(rq, 4); > + if (IS_ERR(cs)) { > + i915_request_add(rq); > + return cs; > + } > + > + *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; > + *cs++ = 0xA300; /* CTX_INFO */ > + *cs++ = ce->timeline->hwsp_offset + 8; > + *cs++ = 0; > + intel_ring_advance(rq, cs); > + > + result = rq->hwsp_seqno + 2; > + i915_request_add(rq); > + > + return result; > +} > + > +int live_rc6_ctx(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct intel_engine_cs *engine; > + enum intel_engine_id id; > + > + /* A read of CTX_INFO upsets rc6. Poke the bear! */ > + > + for_each_engine(engine, gt, id) { I guess we really want to randomise this order so that we don't test the same pattern of reads and fixup everytime. -Chris
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index f7c0baeb3793..0de35d18a2b2 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -777,3 +777,7 @@ u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg) { return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000); } + +#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) +#include "selftest_rc6.c" +#endif diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c index d1752f15702a..1d5bf93d1258 100644 --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c @@ -6,6 +6,7 @@ */ #include "selftest_llc.h" +#include "selftest_rc6.h" static int live_gt_resume(void *arg) { @@ -58,3 +59,15 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915) return intel_gt_live_subtests(tests, &i915->gt); } + +int intel_gt_pm_late_selftests(struct drm_i915_private *i915) +{ + static const struct i915_subtest tests[] = { + SUBTEST(live_rc6_ctx), + }; + + if (intel_gt_is_wedged(&i915->gt)) + return 0; + + return intel_gt_live_subtests(tests, &i915->gt); +} diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c new file mode 100644 index 000000000000..9b02016c81a9 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c @@ -0,0 +1,89 @@ +/* + * SPDX-License-Identifier: MIT + * + * Copyright © 2019 Intel Corporation + */ + +#include "intel_context.h" +#include "intel_engine_pm.h" +#include "intel_gt_requests.h" +#include "intel_ring.h" +#include "selftest_rc6.h" + +static const u32 *__live_rc6_ctx(struct intel_context *ce) +{ + struct i915_request *rq; + u32 const *result; + u32 *cs; + + rq = intel_context_create_request(ce); + if (IS_ERR(rq)) + return ERR_CAST(rq); + + cs = intel_ring_begin(rq, 4); + if (IS_ERR(cs)) { + i915_request_add(rq); + return cs; + } + + *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; + *cs++ = 0xA300; /* CTX_INFO */ + *cs++ = ce->timeline->hwsp_offset + 8; + *cs++ = 0; + intel_ring_advance(rq, cs); + + result = rq->hwsp_seqno + 2; + i915_request_add(rq); + + return result; +} + +int live_rc6_ctx(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + + /* A read of CTX_INFO upsets rc6. Poke the bear! */ + + for_each_engine(engine, gt, id) { + int pass; + + for (pass = 0; pass < 2; pass++) { + struct intel_context *ce; + unsigned int resets = + i915_reset_engine_count(>->i915->gpu_error, + engine); + const u32 *res; + + /* Use a sacrifical context */ + ce = intel_context_create(engine->kernel_context->gem_context, + engine); + if (IS_ERR(ce)) + return PTR_ERR(ce); + + intel_engine_pm_get(engine); + res = __live_rc6_ctx(ce); + intel_engine_pm_put(engine); + intel_context_put(ce); + if (IS_ERR(res)) + return PTR_ERR(res); + + intel_gt_retire_requests(gt); + intel_gt_pm_wait_for_idle(gt); + + pr_debug("%s: CTX_INFO=%0x\n", + engine->name, READ_ONCE(*res)); + if (resets != + i915_reset_engine_count(>->i915->gpu_error, + engine)) { + pr_err("%s: GPU reset required\n", + engine->name); + add_taint_for_CI(TAINT_WARN); + return -EIO; + } + } + } + + return 0; +} diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.h b/drivers/gpu/drm/i915/gt/selftest_rc6.h new file mode 100644 index 000000000000..230c6b4c7dc0 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.h @@ -0,0 +1,12 @@ +/* + * SPDX-License-Identifier: MIT + * + * Copyright © 2019 Intel Corporation + */ + +#ifndef SELFTEST_RC6_H +#define SELFTEST_RC6_H + +int live_rc6_ctx(void *arg); + +#endif /* SELFTEST_RC6_H */ diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h index 4b3cac73e291..db5565679045 100644 --- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h +++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h @@ -38,3 +38,4 @@ selftest(hangcheck, intel_hangcheck_live_selftests) selftest(execlists, intel_execlists_live_selftests) selftest(guc, intel_guc_live_selftest) selftest(perf, i915_perf_live_selftests) +selftest(late_gt_pm, intel_gt_pm_late_selftests)
Reading from CTX_INFO upsets rc6, requiring us to detect and prevent possible rc6 context corruption. Poke at the bear! Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Imre Deak <imre.deak@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_rc6.c | 4 + drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 13 +++ drivers/gpu/drm/i915/gt/selftest_rc6.c | 89 +++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_rc6.h | 12 +++ .../drm/i915/selftests/i915_live_selftests.h | 1 + 5 files changed, 119 insertions(+) create mode 100644 drivers/gpu/drm/i915/gt/selftest_rc6.c create mode 100644 drivers/gpu/drm/i915/gt/selftest_rc6.h