| Message ID | 1574175222-52858-9-git-send-email-biju.das@bp.renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Nobuhiro Iwamatsu |
| Headers | show |
| Series | Add SYS-DMAC/GPIO/AVB/SMP/SCIF/HSCIF/I2C/IIC/CMT/RWDT support | expand |
Hi! > commit f1546da8a5c8862d1e66835affcfaf9a0c123abc upstream. > > Add DT node for the Advanced Power Management Unit (APMU), add the > second CPU core, and use "renesas,apmu" as "enable-method". > > Also add cpu1 phandle node to the PMU interrupt-affinity property. > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > [biju: removed resets property. Updated power-domains and clocks properties] > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > --- > arch/arm/boot/dts/r8a7744.dtsi | 38 ++++++++++++++++++++++++++++++++------ > 1 file changed, 32 insertions(+), 6 deletions(-) > + clocks = <&cpg_clocks R8A7744_CLK_Z>; > + clock-latency = <300000>; /* 300 us */ > + power-domains = <&cpg_clocks>; > + next-level-cache = <&L2_CA15>; > + > + /* kHz - uV - OPPs unknown yet */ > + operating-points = <1500000 1000000>, > + <1312500 1000000>, > + <1125000 1000000>, > + < 937500 1000000>, > + < 750000 1000000>, > + < 375000 1000000>; > + }; Does this mean this is working progress and voltages will be lowered for lower frequencies as testing proceeds? Best regards, Pavel
HI Pavel, Thanks for the feedback. > Subject: Re: [PATCH 4.4.y-cip 08/17] ARM: dts: r8a7744: Add SMP support > > Hi! > > > commit f1546da8a5c8862d1e66835affcfaf9a0c123abc upstream. > > > > Add DT node for the Advanced Power Management Unit (APMU), add the > > second CPU core, and use "renesas,apmu" as "enable-method". > > > > Also add cpu1 phandle node to the PMU interrupt-affinity property. > > > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > > [biju: removed resets property. Updated power-domains and clocks > > properties] > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > > --- > > arch/arm/boot/dts/r8a7744.dtsi | 38 > > ++++++++++++++++++++++++++++++++------ > > 1 file changed, 32 insertions(+), 6 deletions(-) > > > > + clocks = <&cpg_clocks R8A7744_CLK_Z>; > > + clock-latency = <300000>; /* 300 us */ > > + power-domains = <&cpg_clocks>; > > + next-level-cache = <&L2_CA15>; > > + > > + /* kHz - uV - OPPs unknown yet */ > > + operating-points = <1500000 1000000>, > > + <1312500 1000000>, > > + <1125000 1000000>, > > + < 937500 1000000>, > > + < 750000 1000000>, > > + < 375000 1000000>; > > + }; > > Does this mean this is working progress and voltages will be lowered for > lower frequencies as testing proceeds? It supports only DFS not DVFS(ie, by controlling CPUFREQ register you can control the CPU frequency.) Regards, Biju
Hi! > > > + clock-latency = <300000>; /* 300 us */ > > > + power-domains = <&cpg_clocks>; > > > + next-level-cache = <&L2_CA15>; > > > + > > > + /* kHz - uV - OPPs unknown yet */ > > > + operating-points = <1500000 1000000>, > > > + <1312500 1000000>, > > > + <1125000 1000000>, > > > + < 937500 1000000>, > > > + < 750000 1000000>, > > > + < 375000 1000000>; > > > + }; > > > > Does this mean this is working progress and voltages will be lowered for > > lower frequencies as testing proceeds? > > It supports only DFS not DVFS(ie, by controlling CPUFREQ register you can control the CPU frequency.) If it does not support voltage scaling, is the /* kHz - uV - OPPs unknown yet */ comment up-to-date? Would something like /* hardware does not support voltage scaling */ be more useful? Best regards, Pavel
> -----Original Message----- > From: Pavel Machek <pavel@denx.de> > Sent: Wednesday, November 20, 2019 2:44 PM > To: Biju Das <biju.das@bp.renesas.com> > Cc: Pavel Machek <pavel@denx.de>; cip-dev@lists.cip-project.org; Nobuhiro > Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Chris Paterson > <Chris.Paterson2@renesas.com>; Fabrizio Castro > <fabrizio.castro@bp.renesas.com> > Subject: Re: [PATCH 4.4.y-cip 08/17] ARM: dts: r8a7744: Add SMP support > > Hi! > > > > > + clock-latency = <300000>; /* 300 us */ > > > > + power-domains = <&cpg_clocks>; > > > > + next-level-cache = <&L2_CA15>; > > > > + > > > > + /* kHz - uV - OPPs unknown yet */ > > > > + operating-points = <1500000 1000000>, > > > > + <1312500 1000000>, > > > > + <1125000 1000000>, > > > > + < 937500 1000000>, > > > > + < 750000 1000000>, > > > > + < 375000 1000000>; > > > > + }; > > > > > > Does this mean this is working progress and voltages will be lowered > > > for lower frequencies as testing proceeds? > > > > It supports only DFS not DVFS(ie, by controlling CPUFREQ register you > > can control the CPU frequency.) > > If it does not support voltage scaling, is the /* kHz - uV - OPPs unknown yet > */ comment up-to-date? Would something like /* hardware does not > support voltage scaling */ be more useful? Yes true. As per the manual, " Automatic transmission for PMIC control (DVFS) is not available because the RZ/G series products do not support the DVFS function". So we need to fix this upstream first and later backport to cip kernel. Regards, Biju
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index b0c4be2..e712b13 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -48,6 +48,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -68,6 +69,25 @@ < 375000 1000000>; }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1500000000>; + clocks = <&cpg_clocks R8A7744_CLK_Z>; + clock-latency = <300000>; /* 300 us */ + power-domains = <&cpg_clocks>; + next-level-cache = <&L2_CA15>; + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + }; + L2_CA15: cache-controller-0 { compatible = "cache"; cache-unified; @@ -95,7 +115,7 @@ compatible = "arm,cortex-a15-pmu"; interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>; + interrupt-affinity = <&cpu0>, <&cpu1>; }; /* External SCIF clock */ @@ -231,6 +251,12 @@ reg = <0 0xe6060000 0 0x250>; }; + apmu@e6152000 { + compatible = "renesas,r8a7744-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + rst: reset-controller@e6160000 { compatible = "renesas,r8a7744-rst"; reg = <0 0xe6160000 0 0x100>; @@ -454,7 +480,7 @@ interrupt-controller; reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&mstp4_clks R8A7744_CLK_INTC_SYS>; clock-names = "clk"; power-domains = <&cpg_clocks>; @@ -918,10 +944,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; /* External USB clock - can be overridden by the board */