diff mbox series

[v6] drm/i915/tgl: Implement Wa_1604555607

Message ID 20191128021005.3350-1-ramalingam.c@intel.com (mailing list archive)
State New, archived
Headers show
Series [v6] drm/i915/tgl: Implement Wa_1604555607 | expand

Commit Message

Ramalingam C Nov. 28, 2019, 2:10 a.m. UTC 
From: Michel Thierry <michel.thierry@intel.com>

Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.

At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.

v2: Rebased on top of the WA refactoring (Oscar)
v3: Correctly add to ctx_workarounds_init (Michel)
v4:
  uncore read is used [Tvrtko]
  Macros as used for MASK definition [Chris]
v5:
  Skip the Wa_1604555607 verification [Ram]
  i915 ptr retrieved from engine. [Tvrtko]
v6:
  Added wa_add as a wrapper for __wa_add [Chris]
  wa_add is directly called instead of new wrapper [tvrtko]

BSpec: 19363
HSDES: 1604555607
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> [v5]
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 29 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h             |  4 +++
 2 files changed, 29 insertions(+), 4 deletions(-)

Comments

Tvrtko Ursulin Nov. 28, 2019, 10 a.m. UTC | #1 
On 28/11/2019 02:10, Ramalingam C wrote:
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> FF_MODE2 is part of the register state context, that's why it is
> implemented here.
> 
> At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> disabling the WA verification.
> 
> v2: Rebased on top of the WA refactoring (Oscar)
> v3: Correctly add to ctx_workarounds_init (Michel)
> v4:
>    uncore read is used [Tvrtko]
>    Macros as used for MASK definition [Chris]
> v5:
>    Skip the Wa_1604555607 verification [Ram]
>    i915 ptr retrieved from engine. [Tvrtko]
> v6:
>    Added wa_add as a wrapper for __wa_add [Chris]
>    wa_add is directly called instead of new wrapper [tvrtko]
> 
> BSpec: 19363
> HSDES: 1604555607
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> [v5]

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko

> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 29 ++++++++++++++++++---
>   drivers/gpu/drm/i915/i915_reg.h             |  4 +++
>   2 files changed, 29 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 399acae2f33f..722973e09186 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -146,20 +146,26 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
>   	}
>   }
>   
> -static void
> -wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> -		   u32 val)
> +static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +		   u32 val, u32 read_mask)
>   {
>   	struct i915_wa wa = {
>   		.reg  = reg,
>   		.mask = mask,
>   		.val  = val,
> -		.read = mask,
> +		.read = read_mask,
>   	};
>   
>   	_wa_add(wal, &wa);
>   }
>   
> +static void
> +wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +		   u32 val)
> +{
> +	wa_add(wal, reg, mask, val, mask);
> +}
> +
>   static void
>   wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
>   {
> @@ -568,9 +574,24 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>   				     struct i915_wa_list *wal)
>   {
> +	u32 val;
> +
>   	/* Wa_1409142259:tgl */
>   	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>   			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> +
> +	/* Wa_1604555607:tgl */
> +	val = intel_uncore_read(engine->uncore, FF_MODE2);
> +	val &= ~FF_MODE2_TDS_TIMER_MASK;
> +	val |= FF_MODE2_TDS_TIMER_128;
> +	/*
> +	 * FIXME: FF_MODE2 register is not readable till TGL B0. We can
> +	 * enable verification of WA from the later steppings, which enables
> +	 * the read of FF_MODE2.
> +	 */
> +	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> +	       IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
> +			    FF_MODE2_TDS_TIMER_MASK);
>   }
>   
>   static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 94d0f593eeb7..a99fdf8ea53b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7922,6 +7922,10 @@ enum {
>   #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
>   #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
>   
> +#define FF_MODE2			_MMIO(0x6604)
> +#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
> +#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
> +
>   /* PCH */
>   
>   #define PCH_DISPLAY_BASE	0xc0000u
>
Tvrtko Ursulin Nov. 29, 2019, 11:49 a.m. UTC | #2 
On 28/11/2019 03:17, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/tgl: Implement Wa_1604555607
> URL   : https://patchwork.freedesktop.org/series/70134/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_7434 -> Patchwork_15481
> ====================================================
> 
> Summary
> -------
> 
>    **SUCCESS**
> 
>    No regressions found.
> 
>    External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15481/index.html
> 
> Known issues
> ------------
> 
>    Here are the changes found in Patchwork_15481 that come from known issues:
> 
> ### IGT changes ###
> 
> #### Possible fixes ####
> 
>    * igt@i915_module_load@reload-no-display:
>      - fi-skl-lmem:        [DMESG-WARN][1] ([fdo#112261]) -> [PASS][2]
>     [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
>     [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15481/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
> 
>    * igt@i915_module_load@reload-with-fault-injection:
>      - fi-icl-u3:          [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4]
>     [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-icl-u3/igt@i915_module_load@reload-with-fault-injection.html
>     [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15481/fi-icl-u3/igt@i915_module_load@reload-with-fault-injection.html
> 
>    * igt@i915_pm_rpm@module-reload:
>      - fi-skl-6770hq:      [DMESG-WARN][5] ([fdo#112261]) -> [PASS][6]
>     [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
>     [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15481/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
> 
>    * igt@i915_selftest@live_blt:
>      - fi-hsw-peppy:       [DMESG-FAIL][7] ([fdo#112147]) -> [PASS][8]
>     [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-hsw-peppy/igt@i915_selftest@live_blt.html
>     [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15481/fi-hsw-peppy/igt@i915_selftest@live_blt.html
> 
>    * igt@i915_selftest@live_gt_heartbeat:
>      - {fi-kbl-7560u}:     [DMESG-FAIL][9] -> [PASS][10]
>     [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-7560u/igt@i915_selftest@live_gt_heartbeat.html
>     [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15481/fi-kbl-7560u/igt@i915_selftest@live_gt_heartbeat.html
> 
>    
> #### Warnings ####
> 
>    * igt@gem_exec_suspend@basic-s4-devices:
>      - fi-kbl-x1275:       [DMESG-WARN][11] ([fdo#103558] / [fdo#105602] / [fdo#107139]) -> [DMESG-WARN][12] ([fdo#103558] / [fdo#105602] / [fdo#105763] / [fdo#107139])
>     [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html
>     [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15481/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html
> 
>    * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
>      - fi-kbl-x1275:       [DMESG-WARN][13] ([fdo#103558] / [fdo#105602] / [fdo#105763]) -> [DMESG-WARN][14] ([fdo#103558] / [fdo#105602]) +2 similar issues
>     [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
>     [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15481/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
> 
>    * igt@kms_force_connector_basic@force-edid:
>      - fi-kbl-x1275:       [DMESG-WARN][15] ([fdo#103558] / [fdo#105602]) -> [DMESG-WARN][16] ([fdo#103558] / [fdo#105602] / [fdo#105763]) +2 similar issues
>     [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
>     [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15481/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
> 
>    
>    {name}: This element is suppressed. This means it is ignored when computing
>            the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>    [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
>    [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
>    [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
>    [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
>    [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
>    [fdo#112147]: https://bugs.freedesktop.org/show_bug.cgi?id=112147
>    [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261
> 
> 
> Participating hosts (52 -> 45)
> ------------------------------
> 
>    Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
> 
> 
> Build changes
> -------------
> 
>    * CI: CI-20190529 -> None
>    * Linux: CI_DRM_7434 -> Patchwork_15481
> 
>    CI-20190529: 20190529
>    CI_DRM_7434: 1bbc4d30ca9fd950cbcb73f324e00d0bc357758e @ git://anongit.freedesktop.org/gfx-ci/linux
>    IGT_5312: 851c75531043cd906e028632b64b02b9312e9945 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>    Patchwork_15481: f48683f02ed4535aceb6565f477d2dc08479ce8f @ git://anongit.freedesktop.org/gfx-ci/linux
> 
> 
> == Linux commits ==
> 
> f48683f02ed4 drm/i915/tgl: Implement Wa_1604555607

Pushed.

Regards,

Tvrtko
Ramalingam C Nov. 29, 2019, noon UTC | #3 
On 2019-11-29 at 11:49:24 +0000, Tvrtko Ursulin wrote:
> 
> On 28/11/2019 03:17, Patchwork wrote:
> > == Series Details ==
> > 
> > Series: drm/i915/tgl: Implement Wa_1604555607
> > URL   : https://patchwork.freedesktop.org/series/70134/
> > State : success
> > 
<snip>
> > 
> > 
> > == Linux commits ==
> > 
> > f48683f02ed4 drm/i915/tgl: Implement Wa_1604555607
> 
> Pushed.
Thanks Tvrtko!

-Ram
> 
> Regards,
> 
> Tvrtko
> 
> 
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 399acae2f33f..722973e09186 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -146,20 +146,26 @@  static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
 	}
 }
 
-static void
-wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
-		   u32 val)
+static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val, u32 read_mask)
 {
 	struct i915_wa wa = {
 		.reg  = reg,
 		.mask = mask,
 		.val  = val,
-		.read = mask,
+		.read = read_mask,
 	};
 
 	_wa_add(wal, &wa);
 }
 
+static void
+wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val)
+{
+	wa_add(wal, reg, mask, val, mask);
+}
+
 static void
 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 {
@@ -568,9 +574,24 @@  static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
+	u32 val;
+
 	/* Wa_1409142259:tgl */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+
+	/* Wa_1604555607:tgl */
+	val = intel_uncore_read(engine->uncore, FF_MODE2);
+	val &= ~FF_MODE2_TDS_TIMER_MASK;
+	val |= FF_MODE2_TDS_TIMER_128;
+	/*
+	 * FIXME: FF_MODE2 register is not readable till TGL B0. We can
+	 * enable verification of WA from the later steppings, which enables
+	 * the read of FF_MODE2.
+	 */
+	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
+	       IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
+			    FF_MODE2_TDS_TIMER_MASK);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94d0f593eeb7..a99fdf8ea53b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7922,6 +7922,10 @@  enum {
 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
 #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
 
+#define FF_MODE2			_MMIO(0x6604)
+#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
+#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
+
 /* PCH */
 
 #define PCH_DISPLAY_BASE	0xc0000u