| Message ID | 20191203114743.1294-3-nsaenzjulienne@suse.de (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | Raspberry Pi 4 PCIe support | expand |
Thanks for your effort! System can have USB with this patch series, if the device tree is modified properly.
Here is the question: Will not the device tree "scb/ranges" in this patch conflict with commit be8af7a9e3cc ("ARM: dts: bcm2711-rpi-4: Enable GENET support")?
Jian-Hong Pan
Hi Jian-Hong, On Mon, 2019-12-16 at 14:46 +0800, Jian-Hong Pan wrote: > Thanks for your effort! System can have USB with this patch series, if the :) > device tree is modified properly. > Here is the question: Will not the device tree "scb/ranges" in this patch > conflict with commit be8af7a9e3cc ("ARM: dts: bcm2711-rpi-4: Enable GENET > support")? You're right, the patch needs to be refreshed. I'm going to send a v5 of the series factoring out all the log2.h changes, and addressing this. Regards, Nicolas
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index 667658497898..5b61cd915f2b 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -288,6 +288,43 @@ IRQ_TYPE_LEVEL_LOW)>, arm,cpu-registers-not-fw-configured; }; + scb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, + <0x6 0x00000000 0x6 0x00000000 0x40000000>; + + pcie0: pcie@7d500000 { + compatible = "brcm,bcm2711-pcie"; + reg = <0x0 0x7d500000 0x9310>; + device_type = "pci"; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 + IRQ_TYPE_LEVEL_HIGH>; + msi-controller; + msi-parent = <&pcie0>; + + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 + 0x0 0x04000000>; + /* + * The wrapper around the PCIe block has a bug + * preventing it from accessing beyond the first 3GB of + * memory. + */ + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 + 0x0 0xc0000000>; + brcm,enable-ssc; + }; + }; + cpus: cpus { #address-cells = <1>; #size-cells = <0>;
This enables bcm2711's PCIe bus, which is hardwired to a VIA Technologies XHCI USB 3.0 controller. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> --- Changes since v3: - Remove unwarranted comment Changes since v2: - Remove unused interrupt-map - correct dma-ranges to it's full size, non power of 2 bus DMA constraints now supported in linux-next[1] - add device_type - rename alias from pcie_0 to pcie0 Changes since v1: - remove linux,pci-domain arch/arm/boot/dts/bcm2711.dtsi | 37 ++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+)