Message ID | aa8557d53c1f6d3265e2b2c9bc4e127eddb995ea.1575914822.git.alistair.francis@wdc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add RISC-V Hypervisor Extension v0.5 | expand |
On Mon, 09 Dec 2019 10:10:43 PST (-0800), Alistair Francis wrote: > The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access. > Now that we don't use atomics for MIP we can change this back to a xlen > CSR. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 2 +- > target/riscv/cpu.h | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index d37861a430..e521ebe2e1 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -224,7 +224,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > #ifndef CONFIG_USER_ONLY > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); > - qemu_fprintf(f, " %s 0x%x\n", "mip ", env->mip); > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index e59343e13c..f889427869 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -121,7 +121,7 @@ struct CPURISCVState { > target_ulong mhartid; > target_ulong mstatus; > > - uint32_t mip; > + target_ulong mip; > uint32_t miclaim; > > target_ulong mie; Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
On Thu, Jan 2, 2020 at 10:18 AM Palmer Dabbelt <palmerdabbelt@google.com> wrote: > > On Mon, 09 Dec 2019 10:10:43 PST (-0800), Alistair Francis wrote: > > The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access. > > Now that we don't use atomics for MIP we can change this back to a xlen > > CSR. > > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > > --- > > target/riscv/cpu.c | 2 +- > > target/riscv/cpu.h | 2 +- > > 2 files changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index d37861a430..e521ebe2e1 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -224,7 +224,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > > #ifndef CONFIG_USER_ONLY > > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); > > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); > > - qemu_fprintf(f, " %s 0x%x\n", "mip ", env->mip); > > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); > > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); > > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); > > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index e59343e13c..f889427869 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -121,7 +121,7 @@ struct CPURISCVState { > > target_ulong mhartid; > > target_ulong mstatus; > > > > - uint32_t mip; > > + target_ulong mip; > > uint32_t miclaim; > > > > target_ulong mie; > > Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Thanks! Can you just apply the patches from this series as they are reviewed? Also, can you review this series :) Alistair
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d37861a430..e521ebe2e1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -224,7 +224,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); - qemu_fprintf(f, " %s 0x%x\n", "mip ", env->mip); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e59343e13c..f889427869 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -121,7 +121,7 @@ struct CPURISCVState { target_ulong mhartid; target_ulong mstatus; - uint32_t mip; + target_ulong mip; uint32_t miclaim; target_ulong mie;
The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access. Now that we don't use atomics for MIP we can change this back to a xlen CSR. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)