| Message ID | 1578933813-80122-5-git-send-email-zhouyanjie@wanyeetech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Paul Burton |
| Headers | show |
| Series | Introduce SMP support for JZ4780. | expand |
14.01.2020, 00:44, "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>: > Document the available properties for the SoC root node and the > CPU nodes of the devicetree for the Ingenic XBurst SoCs. > > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> > --- > .../bindings/mips/ingenic/ingenic,cpu.txt | 32 ++++++++++++++++++++++ > .../bindings/mips/ingenic/ingenic,soc,txt | 18 ++++++++++++ > 2 files changed, 50 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt > create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt > We'd better use schemas for the document. See[1] Thanks. [1]: https://lwn.net/Articles/771621/ -- Jiaxun Yang
Hi Jiaxun, On 2020年01月14日 12:59, Jiaxun Yang wrote: > > 14.01.2020, 00:44, "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>: >> Document the available properties for the SoC root node and the >> CPU nodes of the devicetree for the Ingenic XBurst SoCs. >> >> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> >> --- >> .../bindings/mips/ingenic/ingenic,cpu.txt | 32 ++++++++++++++++++++++ >> .../bindings/mips/ingenic/ingenic,soc,txt | 18 ++++++++++++ >> 2 files changed, 50 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt >> create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt >> > We'd better use schemas for the document. I will change it in v2. Thanks and best regards! > > See[1] > > Thanks. > > [1]: https://lwn.net/Articles/771621/ > -- > Jiaxun Yang
diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt new file mode 100644 index 00000000..f23e9be --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt @@ -0,0 +1,32 @@ +Bindings for Ingenic XBurst family CPUs. + +Required properties: +- device_type: Must be "cpu". +- compatible: One of: + - "ingenic,xburst". + - "ingenic,xburst2". +- reg: The number of the CPU. + +Example: +cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "ingenic,xburst"; + reg = <0>; + + clocks = <&cgu JZ4780_CLK_CPU>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "ingenic,xburst"; + reg = <1>; + + clocks = <&cgu JZ4780_CLK_CORE1>; + clock-names = "cpu"; + }; +}; diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt new file mode 100644 index 00000000..c731fa3 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt @@ -0,0 +1,18 @@ +Bindings for Ingenic SoCs with XBurst CPU inside. + +Required properties: +- compatible: One of: + - "ingenic,jz4740". + - "ingenic,jz4725b". + - "ingenic,jz4760". + - "ingenic,jz4760b". + - "ingenic,jz4770". + - "ingenic,jz4780". + - "ingenic,x1000". + - "ingenic,x1000e". + - "ingenic,x1500". + +Example: +#address-cells = <1>; +#size-cells = <1>; +compatible = "ingenic,jz4780";
Document the available properties for the SoC root node and the CPU nodes of the devicetree for the Ingenic XBurst SoCs. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> --- .../bindings/mips/ingenic/ingenic,cpu.txt | 32 ++++++++++++++++++++++ .../bindings/mips/ingenic/ingenic,soc,txt | 18 ++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt