| Message ID | 20200213154759.3641671-1-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/gt: Ensure 'ENABLE_BOOT_FETCH' is enabled before ppGTT | expand |
On Thu, Feb 13, 2020 at 03:47:59PM +0000, Chris Wilson wrote: > Cryptic notes in bspec say that "The MBC Driver Boot Enable bit in MBCTL > register must be set before this register is written to upon boot up > (including S3 exit)." > > We tried adding it to our list of verified workarounds, but our > self checks spot that the bit does not stick. It's only meant to be > cleared after a FLR. As it fails our verification, just blindly apply > the bit prior to loading the ppGTT. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_ring_submission.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > index f70b903a98bc..e41a329d435a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -642,6 +642,9 @@ static void set_pp_dir(struct intel_engine_cs *engine) > if (vm) { > struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); > > + intel_uncore_rmw(engine->uncore, GEN6_MBCTL, > + 0, GEN6_MBCTL_ENABLE_BOOT_FETCH) Wasn't setting this bit implicated in some regressions long ago? > + > ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G); > ENGINE_WRITE(engine, RING_PP_DIR_BASE, > px_base(ppgtt->pd)->ggtt_offset << 10); > -- > 2.25.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting Ville Syrjälä (2020-02-13 17:57:56) > On Thu, Feb 13, 2020 at 03:47:59PM +0000, Chris Wilson wrote: > > Cryptic notes in bspec say that "The MBC Driver Boot Enable bit in MBCTL > > register must be set before this register is written to upon boot up > > (including S3 exit)." > > > > We tried adding it to our list of verified workarounds, but our > > self checks spot that the bit does not stick. It's only meant to be > > cleared after a FLR. As it fails our verification, just blindly apply > > the bit prior to loading the ppGTT. > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_ring_submission.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > > index f70b903a98bc..e41a329d435a 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > > @@ -642,6 +642,9 @@ static void set_pp_dir(struct intel_engine_cs *engine) > > if (vm) { > > struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); > > > > + intel_uncore_rmw(engine->uncore, GEN6_MBCTL, > > + 0, GEN6_MBCTL_ENABLE_BOOT_FETCH) > > Wasn't setting this bit implicated in some regressions long ago? commit 3414caf63421762e57b26aa999e5187b42ee1606 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Wed Aug 21 08:08:55 2013 -0700 drm/i915: drop WaMbcDriverBootEnable workaround Turns out the BIOS will do this for us as needed, and if we try to do it again we risk hangs or other bad behavior. Note that this seems to break libva on ChromeOS after resumes (but strangely _not_ after booting up). This essentially reverts commit b4ae3f22d238617ca11610b29fde16cf8c0bc6e0 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Thu Jun 14 11:04:48 2012 -0700 drm/i915: load boot context at driver init time and commit b3bf076697a68a8577f4a5f7407de0bb2b3b56ac Author: Paulo Zanoni <paulo.r.zanoni@intel.com> Date: Tue Nov 20 13:27:44 2012 -0200 drm/i915: implement WaMbcDriverBootEnable on Haswell Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reported-and-Tested-by: Stéphane Marchesin <marcheu@chromium.org>
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index f70b903a98bc..e41a329d435a 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -642,6 +642,9 @@ static void set_pp_dir(struct intel_engine_cs *engine) if (vm) { struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); + intel_uncore_rmw(engine->uncore, GEN6_MBCTL, + 0, GEN6_MBCTL_ENABLE_BOOT_FETCH) + ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G); ENGINE_WRITE(engine, RING_PP_DIR_BASE, px_base(ppgtt->pd)->ggtt_offset << 10);
Cryptic notes in bspec say that "The MBC Driver Boot Enable bit in MBCTL register must be set before this register is written to upon boot up (including S3 exit)." We tried adding it to our list of verified workarounds, but our self checks spot that the bit does not stick. It's only meant to be cleared after a FLR. As it fails our verification, just blindly apply the bit prior to loading the ppGTT. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_ring_submission.c | 3 +++ 1 file changed, 3 insertions(+)