Message ID | 20200219005414.15635-1-david@gibson.dropbear.id.au (mailing list archive) |
---|---|
Headers | show |
Series | target/ppc: Correct some errors with real mode handling | expand |
Patchew URL: https://patchew.org/QEMU/20200219005414.15635-1-david@gibson.dropbear.id.au/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH v3 00/12] target/ppc: Correct some errors with real mode handling Message-id: 20200219005414.15635-1-david@gibson.dropbear.id.au Type: series === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === From https://github.com/patchew-project/qemu * [new tag] patchew/20200219005414.15635-1-david@gibson.dropbear.id.au -> patchew/20200219005414.15635-1-david@gibson.dropbear.id.au Switched to a new branch 'test' 275db2f target/ppc: Don't store VRMA SLBE persistently 8f4ef78 target/ppc: Streamline construction of VRMA SLB entry 5329f3b target/ppc: Only calculate RMLS derived RMA limit on demand 656a372 target/ppc: Correct RMLS table 6432e7f target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] 00f78cd target/ppc: Use class fields to simplify LPCR masking c6f6cea target/ppc: Remove RMOR register from POWER9 & POWER10 c6daae6 spapr, ppc: Remove VPM0/RMLS hacks for POWER9 3374197 target/ppc: Introduce ppc_hash64_use_vrma() helper 7e14e97 target/ppc: Correct handling of real mode accesses with vhyp on hash MMU 7c298cb ppc: Remove stub of PPC970 HID4 implementation 4525879 ppc: Remove stub support for 32-bit hypervisor mode === OUTPUT BEGIN === 1/12 Checking commit 4525879e6fae (ppc: Remove stub support for 32-bit hypervisor mode) 2/12 Checking commit 7c298cb58821 (ppc: Remove stub of PPC970 HID4 implementation) WARNING: Block comments use a leading /* on a separate line #98: FILE: target/ppc/translate_init.inc.c:7904: + /* PPC970: HID4 covers things later controlled by the LPCR and WARNING: Block comments use a trailing */ on a separate line #102: FILE: target/ppc/translate_init.inc.c:7908: + * ignore it */ total: 0 errors, 2 warnings, 71 lines checked Patch 2/12 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 3/12 Checking commit 7e14e97fa725 (target/ppc: Correct handling of real mode accesses with vhyp on hash MMU) 4/12 Checking commit 337419739ee8 (target/ppc: Introduce ppc_hash64_use_vrma() helper) WARNING: Block comments use a leading /* on a separate line #41: FILE: target/ppc/mmu-hash64.c:675: + /* ISAv3.0 (POWER9) always uses VRMA, the VPM0 field and RMOR WARNING: Block comments use a trailing */ on a separate line #42: FILE: target/ppc/mmu-hash64.c:676: + * register no longer exist */ total: 0 errors, 2 warnings, 83 lines checked Patch 4/12 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 5/12 Checking commit c6daae6e9b06 (spapr, ppc: Remove VPM0/RMLS hacks for POWER9) 6/12 Checking commit c6f6ceaa43fc (target/ppc: Remove RMOR register from POWER9 & POWER10) 7/12 Checking commit 00f78cdfebbd (target/ppc: Use class fields to simplify LPCR masking) 8/12 Checking commit 6432e7fe864f (target/ppc: Streamline calculation of RMA limit from LPCR[RMLS]) 9/12 Checking commit 656a372f677c (target/ppc: Correct RMLS table) 10/12 Checking commit 5329f3b07fba (target/ppc: Only calculate RMLS derived RMA limit on demand) 11/12 Checking commit 8f4ef78a4af3 (target/ppc: Streamline construction of VRMA SLB entry) ERROR: braces {} are necessary for all arms of this statement #80: FILE: target/ppc/mmu-hash64.c:1084: + if (build_vrma_slbe(cpu, slb) == 0) [...] total: 1 errors, 0 warnings, 97 lines checked Patch 11/12 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 12/12 Checking commit 275db2fe2a84 (target/ppc: Don't store VRMA SLBE persistently) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20200219005414.15635-1-david@gibson.dropbear.id.au/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to patchew-devel@redhat.com
On Wed, Feb 19, 2020 at 11:54:02AM +1100, David Gibson wrote: > POWER "book S" (server class) cpus have a concept of "real mode" where > MMU translation is disabled... sort of. In fact this can mean a bunch > of slightly different things when hypervisor mode and other > considerations are present. > > We had some errors in edge cases here, so clean some things up and > correct them. Duh. Forgot to run checkpatch, new version coming shortly. > > Changes since v2: > * Removed 32-bit hypervisor stubs more completely > * Minor polish based on review comments > Changes since RFCv1: > * Add a number of extra patches taking advantage of the initial > cleanups > > David Gibson (12): > ppc: Remove stub support for 32-bit hypervisor mode > ppc: Remove stub of PPC970 HID4 implementation > target/ppc: Correct handling of real mode accesses with vhyp on hash > MMU > target/ppc: Introduce ppc_hash64_use_vrma() helper > spapr, ppc: Remove VPM0/RMLS hacks for POWER9 > target/ppc: Remove RMOR register from POWER9 & POWER10 > target/ppc: Use class fields to simplify LPCR masking > target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] > target/ppc: Correct RMLS table > target/ppc: Only calculate RMLS derived RMA limit on demand > target/ppc: Streamline construction of VRMA SLB entry > target/ppc: Don't store VRMA SLBE persistently > > hw/ppc/spapr_cpu_core.c | 6 +- > target/ppc/cpu-qom.h | 1 + > target/ppc/cpu.h | 25 +-- > target/ppc/mmu-hash64.c | 329 ++++++++++++-------------------- > target/ppc/translate_init.inc.c | 60 ++++-- > 5 files changed, 175 insertions(+), 246 deletions(-) >