| Message ID | 20200308094954.13258-1-guoren@kernel.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | riscv: Add vector ISA support | expand |
On Sun, Mar 8, 2020 at 5:50 PM <guoren@kernel.org> wrote: > > From: Guo Ren <guoren@linux.alibaba.com> > > The implementation follow the RISC-V "V" Vector Extension draft v0.8 with > 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1]. > > The patch implement basic context switch, sigcontext save/restore and > ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen > is implemented. We need to discuss about vlen-size for libc sigcontext and > ptrace (the maximum size of vlen is unlimited in spec). > > Puzzle: > Dave Martin has talked "Growing CPU register state without breaking ABI" [2] > before, and riscv also met vlen size problem. Let's discuss the common issue > for all architectures and we need a better solution for unlimited vlen. > > Any help are welcomed :) > > 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3 Hi Guo, Thanks for your patch. It seems the qemu repo doesn't have this branch?
On 2020/3/9 11:41, Greentime Hu wrote: > On Sun, Mar 8, 2020 at 5:50 PM <guoren@kernel.org> wrote: >> From: Guo Ren <guoren@linux.alibaba.com> >> >> The implementation follow the RISC-V "V" Vector Extension draft v0.8 with >> 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1]. >> >> The patch implement basic context switch, sigcontext save/restore and >> ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen >> is implemented. We need to discuss about vlen-size for libc sigcontext and >> ptrace (the maximum size of vlen is unlimited in spec). >> >> Puzzle: >> Dave Martin has talked "Growing CPU register state without breaking ABI" [2] >> before, and riscv also met vlen size problem. Let's discuss the common issue >> for all architectures and we need a better solution for unlimited vlen. >> >> Any help are welcomed :) >> >> 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3 > Hi Guo, > > Thanks for your patch. > It seems the qemu repo doesn't have this branch? Hi Greentime, It's a promise from me. Now it's ready. You can turn on vector by "qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1". Zhiwei
On Mon, Mar 9, 2020 at 6:27 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > On 2020/3/9 11:41, Greentime Hu wrote: > > On Sun, Mar 8, 2020 at 5:50 PM <guoren@kernel.org> wrote: > >> From: Guo Ren <guoren@linux.alibaba.com> > >> > >> The implementation follow the RISC-V "V" Vector Extension draft v0.8 with > >> 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1]. > >> > >> The patch implement basic context switch, sigcontext save/restore and > >> ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen > >> is implemented. We need to discuss about vlen-size for libc sigcontext and > >> ptrace (the maximum size of vlen is unlimited in spec). > >> > >> Puzzle: > >> Dave Martin has talked "Growing CPU register state without breaking ABI" [2] > >> before, and riscv also met vlen size problem. Let's discuss the common issue > >> for all architectures and we need a better solution for unlimited vlen. > >> > >> Any help are welcomed :) > >> > >> 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3 > > Hi Guo, > > > > Thanks for your patch. > > It seems the qemu repo doesn't have this branch? > Hi Greentime, > > It's a promise from me. Now it's ready. You can turn on vector by > "qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1". > > Zhiwei > > Hi Zhiwei, Thank you, I see the branch in the repo now. I will give it a try and let you know if I have any problem. :)
On Tue, Mar 10, 2020 at 4:54 PM Greentime Hu <greentime.hu@sifive.com> wrote: > > On Mon, Mar 9, 2020 at 6:27 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > On 2020/3/9 11:41, Greentime Hu wrote: > > > On Sun, Mar 8, 2020 at 5:50 PM <guoren@kernel.org> wrote: > > >> From: Guo Ren <guoren@linux.alibaba.com> > > >> > > >> The implementation follow the RISC-V "V" Vector Extension draft v0.8 with > > >> 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1]. > > >> > > >> The patch implement basic context switch, sigcontext save/restore and > > >> ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen > > >> is implemented. We need to discuss about vlen-size for libc sigcontext and > > >> ptrace (the maximum size of vlen is unlimited in spec). > > >> > > >> Puzzle: > > >> Dave Martin has talked "Growing CPU register state without breaking ABI" [2] > > >> before, and riscv also met vlen size problem. Let's discuss the common issue > > >> for all architectures and we need a better solution for unlimited vlen. > > >> > > >> Any help are welcomed :) > > >> > > >> 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3 > > > Hi Guo, > > > > > > Thanks for your patch. > > > It seems the qemu repo doesn't have this branch? > > Hi Greentime, > > > > It's a promise from me. Now it's ready. You can turn on vector by > > "qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1". > > > > Zhiwei > > > > > > Hi Zhiwei, > > Thank you, I see the branch in the repo now. I will give it a try and > let you know if I have any problem. :) Hi Zhiwei & Guo, It seems current version only support v0.7.1 in qemu but this patchset is verified in qemu too and it is based on 0.8. Would you please provide the qemu with 0.8 vector spec supported? or Did I miss something? 489 if (cpu->cfg.vext_spec) { 490 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { 491 vext_version = VEXT_VERSION_0_07_1; 492 } else { 493 error_setg(errp, 494 "Unsupported vector spec version '%s'", 495 cpu->cfg.vext_spec); 496 return; 497 } 498 } By the way, can I specify vlen in Qemu? Thank you. :)
On 2020/3/10 17:19, Greentime Hu wrote: > On Tue, Mar 10, 2020 at 4:54 PM Greentime Hu <greentime.hu@sifive.com> wrote: >> On Mon, Mar 9, 2020 at 6:27 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: >>> On 2020/3/9 11:41, Greentime Hu wrote: >>>> On Sun, Mar 8, 2020 at 5:50 PM <guoren@kernel.org> wrote: >>>>> From: Guo Ren <guoren@linux.alibaba.com> >>>>> >>>>> The implementation follow the RISC-V "V" Vector Extension draft v0.8 with >>>>> 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1]. >>>>> >>>>> The patch implement basic context switch, sigcontext save/restore and >>>>> ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen >>>>> is implemented. We need to discuss about vlen-size for libc sigcontext and >>>>> ptrace (the maximum size of vlen is unlimited in spec). >>>>> >>>>> Puzzle: >>>>> Dave Martin has talked "Growing CPU register state without breaking ABI" [2] >>>>> before, and riscv also met vlen size problem. Let's discuss the common issue >>>>> for all architectures and we need a better solution for unlimited vlen. >>>>> >>>>> Any help are welcomed :) >>>>> >>>>> 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3 >>>> Hi Guo, >>>> >>>> Thanks for your patch. >>>> It seems the qemu repo doesn't have this branch? >>> Hi Greentime, >>> >>> It's a promise from me. Now it's ready. You can turn on vector by >>> "qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1". >>> >>> Zhiwei >>> >>> >> Hi Zhiwei, >> >> Thank you, I see the branch in the repo now. I will give it a try and >> let you know if I have any problem. :) > Hi Zhiwei & Guo, > > It seems current version only support v0.7.1 in qemu but this patchset > is verified in qemu too and it is based on 0.8. > Would you please provide the qemu with 0.8 vector spec supported? Hi Greentime, vector-upstream-v3 only supports v0.7.1. It is under reviewed in QEMU community. Maybe I will also support v0.8 after it is merged. As Guo Ren said, the kernel patch set works both for v0.7.1 and v0.8, which only uses the common instructions and CSRs. > or > Did I miss something? > > 489 if (cpu->cfg.vext_spec) { > 490 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { > 491 vext_version = VEXT_VERSION_0_07_1; > 492 } else { > 493 error_setg(errp, > 494 "Unsupported vector spec version '%s'", > 495 cpu->cfg.vext_spec); > 496 return; > 497 } > 498 } > > By the way, can I specify vlen in Qemu? Yes, you can specify vlen through QEMU command line like “-cpu rv64,v=true,vext_spec=v0.7.1,vlen=256” Currently , vlen supports up to 512 bits, with a default value 128 bits. > Thank you. :)
<guoren@kernel.org> 於 2020年3月8日 週日 下午5:50寫道： > > From: Guo Ren <guoren@linux.alibaba.com> > > The implementation follow the RISC-V "V" Vector Extension draft v0.8 with > 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1]. > > The patch implement basic context switch, sigcontext save/restore and > ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen > is implemented. We need to discuss about vlen-size for libc sigcontext and > ptrace (the maximum size of vlen is unlimited in spec). > > Puzzle: > Dave Martin has talked "Growing CPU register state without breaking ABI" [2] > before, and riscv also met vlen size problem. Let's discuss the common issue > for all architectures and we need a better solution for unlimited vlen. > > Any help are welcomed :) > > 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3 > 2: https://blog.linuxplumbersconf.org/2017/ocw/sessions/4671.html > Hi Ren, Thanks for the patch. I have some ideas about the vlen and sigcontext. Since vlen may not be fixed of each RISC-V cores and it could be super big, it means we have to allocate the memory dynamically. In kernel space, we may use a pointer in the context data structure. Something like https://github.com/torvalds/linux/blob/master/arch/arm64/kernel/fpsimd.c#L498 In user space, we need to let user space know the length of vector registers. We may create a special header in sigcontext. Something like https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/sigcontext.h#L36 https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/sigcontext.h#L127 For the implementation in makecontext, swapcontext, getcontext, setcontext of glibc, we may not need to port because it seems to be deprecated? https://stackoverflow.com/questions/4298986/is-there-something-to-replace-the-ucontext-h-functions For the unwinding implementation of libgcc since it needs to know the meaning of data structure is changed. It also need to be port. > --- > Changelog V3 > - Rebase linux-5.6-rc3 and tested with qemu > - Seperate patches with Anup's advice > - Give out a ABI puzzle with unlimited vlen > > Changelog V2 > - Fixup typo "vecotr, fstate_save->vstate_save". > - Fixup wrong saved registers' length in vector.S. > - Seperate unrelated patches from this one. > > Guo Ren (11): > riscv: Separate patch for cflags and aflags > riscv: Rename __switch_to_aux -> fpu > riscv: Extending cpufeature.c to detect V-extension > riscv: Add CSR defines related to VECTOR extension > riscv: Add vector feature to compile > riscv: Add has_vector detect > riscv: Reset vector register > riscv: Add vector struct and assembler definitions > riscv: Add task switch support for VECTOR > riscv: Add ptrace support > riscv: Add sigcontext save/restore > > arch/riscv/Kconfig | 9 ++ > arch/riscv/Makefile | 19 ++- > arch/riscv/include/asm/csr.h | 17 ++- > arch/riscv/include/asm/processor.h | 1 + > arch/riscv/include/asm/switch_to.h | 54 ++++++- > arch/riscv/include/uapi/asm/elf.h | 1 + > arch/riscv/include/uapi/asm/hwcap.h | 1 + > arch/riscv/include/uapi/asm/ptrace.h | 9 ++ > arch/riscv/include/uapi/asm/sigcontext.h | 1 + > arch/riscv/kernel/Makefile | 1 + > arch/riscv/kernel/asm-offsets.c | 187 +++++++++++++++++++++++ > arch/riscv/kernel/cpufeature.c | 12 +- > arch/riscv/kernel/entry.S | 2 +- > arch/riscv/kernel/head.S | 49 +++++- > arch/riscv/kernel/process.c | 10 ++ > arch/riscv/kernel/ptrace.c | 41 +++++ > arch/riscv/kernel/signal.c | 40 +++++ > arch/riscv/kernel/vector.S | 84 ++++++++++ > include/uapi/linux/elf.h | 1 + > 19 files changed, 524 insertions(+), 15 deletions(-) > create mode 100644 arch/riscv/kernel/vector.S > > -- > 2.17.0 >
Hi Greentime, On Mon, Mar 23, 2020 at 12:00 PM Greentime Hu <greentime.hu@sifive.com> wrote: > > <guoren@kernel.org> 於 2020年3月8日 週日 下午5:50寫道： > > > > From: Guo Ren <guoren@linux.alibaba.com> > > > > The implementation follow the RISC-V "V" Vector Extension draft v0.8 with > > 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1]. > > > > The patch implement basic context switch, sigcontext save/restore and > > ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen > > is implemented. We need to discuss about vlen-size for libc sigcontext and > > ptrace (the maximum size of vlen is unlimited in spec). > > > > Puzzle: > > Dave Martin has talked "Growing CPU register state without breaking ABI" [2] > > before, and riscv also met vlen size problem. Let's discuss the common issue > > for all architectures and we need a better solution for unlimited vlen. > > > > Any help are welcomed :) > > > > 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3 > > 2: https://blog.linuxplumbersconf.org/2017/ocw/sessions/4671.html > > > > Hi Ren, > > Thanks for the patch. I have some ideas about the vlen and sigcontext. > Since vlen may not be fixed of each RISC-V cores and it could be super > big, it means we have to allocate the memory dynamically. > In kernel space, we may use a pointer in the context data structure. > Something like https://github.com/torvalds/linux/blob/master/arch/arm64/kernel/fpsimd.c#L498 > In user space, we need to let user space know the length of vector > registers. We may create a special header in sigcontext. Something > like https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/sigcontext.h#L36 > https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/sigcontext.h#L127 As you've mentioned codes above, arm64 use a fixed pre-allocate sigcontext with a large space: struct sigcontext { __u64 fault_address; /* AArch64 registers */ __u64 regs[31]; __u64 sp; __u64 pc; __u64 pstate; /* 4K reserved for FP/SIMD state and future expansion */ __u8 __reserved[4096] __attribute__((__aligned__(16))); }; There are several contexts in the space above: fpsimd, esr, sve, extra __reserved[4096]: * 0x210 fpsimd_context * 0x10 esr_context * 0x8a0 sve_context (vl <= 64) (optional) * 0x20 extra_context (optional) * 0x10 terminator (null _aarch64_ctx) * 0x510 (reserved for future allocation) 0x210 + 0x10 + 0x8a0 + 0x20 + 0x10 + 0x510 = 4096 The max vl is 64 in arm sve, but for riscv want an unlimited size solution and more extensible/flexible solution, such as dynamic allocating user-space context with hwinfo. But there is no ref solution around all arches. There is a choice puzzle for me: 1) A pre-allocated&limited reserved size of sigcontext, the solution has been practiced and we just need to determine the size. 2) Dynamically allocated/unlimited size of sigcontext, but may deal with glibc, libgcc infrastructure on abi view. Before the next stage of work, we need to choose the direction and it's also a common puzzle for all architectures with extending vector/simd like co-processor solutions. ps: Have a look on Dave's patch, he just follow the arm64 fixed pre-allocate limited sigcontext infrastructure: (I don't think it's a proper example for riscv vector design.) commit d0b8cd3187889476144bd9b13bf36a932c3e7952 Author: Dave Martin <Dave.Martin@arm.com> Date: Tue Oct 31 15:51:03 2017 +0000 arm64/sve: Signal frame and context structure definition > > For the implementation in makecontext, swapcontext, getcontext, > setcontext of glibc, we may not need to port because it seems to be > deprecated? > https://stackoverflow.com/questions/4298986/is-there-something-to-replace-the-ucontext-h-functions Agree, we needn't deal with them at beginning. > > For the unwinding implementation of libgcc since it needs to know the > meaning of data structure is changed. It also need to be port. Yes, it'll break the abi and such as the elf with -fexception compiled will be broken.
From: Guo Ren <guoren@linux.alibaba.com> The implementation follow the RISC-V "V" Vector Extension draft v0.8 with 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1]. The patch implement basic context switch, sigcontext save/restore and ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen is implemented. We need to discuss about vlen-size for libc sigcontext and ptrace (the maximum size of vlen is unlimited in spec). Puzzle: Dave Martin has talked "Growing CPU register state without breaking ABI" [2] before, and riscv also met vlen size problem. Let's discuss the common issue for all architectures and we need a better solution for unlimited vlen. Any help are welcomed :) 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3 2: https://blog.linuxplumbersconf.org/2017/ocw/sessions/4671.html --- Changelog V3 - Rebase linux-5.6-rc3 and tested with qemu - Seperate patches with Anup's advice - Give out a ABI puzzle with unlimited vlen Changelog V2 - Fixup typo "vecotr, fstate_save->vstate_save". - Fixup wrong saved registers' length in vector.S. - Seperate unrelated patches from this one. Guo Ren (11): riscv: Separate patch for cflags and aflags riscv: Rename __switch_to_aux -> fpu riscv: Extending cpufeature.c to detect V-extension riscv: Add CSR defines related to VECTOR extension riscv: Add vector feature to compile riscv: Add has_vector detect riscv: Reset vector register riscv: Add vector struct and assembler definitions riscv: Add task switch support for VECTOR riscv: Add ptrace support riscv: Add sigcontext save/restore arch/riscv/Kconfig | 9 ++ arch/riscv/Makefile | 19 ++- arch/riscv/include/asm/csr.h | 17 ++- arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/asm/switch_to.h | 54 ++++++- arch/riscv/include/uapi/asm/elf.h | 1 + arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/include/uapi/asm/ptrace.h | 9 ++ arch/riscv/include/uapi/asm/sigcontext.h | 1 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/asm-offsets.c | 187 +++++++++++++++++++++++ arch/riscv/kernel/cpufeature.c | 12 +- arch/riscv/kernel/entry.S | 2 +- arch/riscv/kernel/head.S | 49 +++++- arch/riscv/kernel/process.c | 10 ++ arch/riscv/kernel/ptrace.c | 41 +++++ arch/riscv/kernel/signal.c | 40 +++++ arch/riscv/kernel/vector.S | 84 ++++++++++ include/uapi/linux/elf.h | 1 + 19 files changed, 524 insertions(+), 15 deletions(-) create mode 100644 arch/riscv/kernel/vector.S