diff mbox series

irqchip/sifive-plic: Fix maximum priority threshold value

Message ID 20200403014609.71831-1-atish.patra@wdc.com (mailing list archive)
State New, archived
Headers show
Series irqchip/sifive-plic: Fix maximum priority threshold value | expand

Commit Message

Atish Patra April 3, 2020, 1:46 a.m. UTC
As per the PLIC specification, maximum priority threshold value is 0x7
not 0xF. Even though it doesn't cause any error in qemu/hifive unleashed,
there may be some implementation which checks the upper bound resulting in
an illegal access.

Fixes: ccbe80bad571 (irqchip/sifive-plic: Enable/Disable external
		     interrupts upon cpu online/offline)
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
 drivers/irqchip/irq-sifive-plic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Marc Zyngier April 11, 2020, 10:59 a.m. UTC | #1
On Thu,  2 Apr 2020 18:46:09 -0700
Atish Patra <atish.patra@wdc.com> wrote:

> As per the PLIC specification, maximum priority threshold value is 0x7
> not 0xF. Even though it doesn't cause any error in qemu/hifive unleashed,
> there may be some implementation which checks the upper bound resulting in
> an illegal access.
> 
> Fixes: ccbe80bad571 (irqchip/sifive-plic: Enable/Disable external
> 		     interrupts upon cpu online/offline)

Small nit: please write the "Fixes:" tag as documented in
process/submitting-patches.rst:

Fixes: ccbe80bad571 ("irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline")

(with quotes, and on a single line), as it otherwise breaks with the
lore-scrapping tooling which a bunch of us are now using.

> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
>  drivers/irqchip/irq-sifive-plic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> index c34fb3ae0ff8..d0a71febdadc 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -56,7 +56,7 @@
>  #define     CONTEXT_THRESHOLD		0x00
>  #define     CONTEXT_CLAIM		0x04
>  
> -#define	PLIC_DISABLE_THRESHOLD		0xf
> +#define	PLIC_DISABLE_THRESHOLD		0x7
>  #define	PLIC_ENABLE_THRESHOLD		0
>  
>  struct plic_priv {

Queued for post -rc1.

Thanks,

	M.
Atish Patra April 13, 2020, 7:16 a.m. UTC | #2
On Sat, Apr 11, 2020 at 3:59 AM Marc Zyngier <maz@kernel.org> wrote:
>
> On Thu,  2 Apr 2020 18:46:09 -0700
> Atish Patra <atish.patra@wdc.com> wrote:
>
> > As per the PLIC specification, maximum priority threshold value is 0x7
> > not 0xF. Even though it doesn't cause any error in qemu/hifive unleashed,
> > there may be some implementation which checks the upper bound resulting in
> > an illegal access.
> >
> > Fixes: ccbe80bad571 (irqchip/sifive-plic: Enable/Disable external
> >                    interrupts upon cpu online/offline)
>
> Small nit: please write the "Fixes:" tag as documented in
> process/submitting-patches.rst:
>
> Fixes: ccbe80bad571 ("irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline")
>
> (with quotes, and on a single line), as it otherwise breaks with the
> lore-scrapping tooling which a bunch of us are now using.
>

Ahh Sorry for that. I will keep that in mind. I broke it into two
lines fearing a checkpatch warning.
But I guess I unleashed a bigger monster unknowingly ;)

> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> >  drivers/irqchip/irq-sifive-plic.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> > index c34fb3ae0ff8..d0a71febdadc 100644
> > --- a/drivers/irqchip/irq-sifive-plic.c
> > +++ b/drivers/irqchip/irq-sifive-plic.c
> > @@ -56,7 +56,7 @@
> >  #define     CONTEXT_THRESHOLD                0x00
> >  #define     CONTEXT_CLAIM            0x04
> >
> > -#define      PLIC_DISABLE_THRESHOLD          0xf
> > +#define      PLIC_DISABLE_THRESHOLD          0x7
> >  #define      PLIC_ENABLE_THRESHOLD           0
> >
> >  struct plic_priv {
>
> Queued for post -rc1.
>
> Thanks,
>
>         M.
> --
> Jazz is not dead. It just smells funny...
>
diff mbox series

Patch

diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index c34fb3ae0ff8..d0a71febdadc 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -56,7 +56,7 @@ 
 #define     CONTEXT_THRESHOLD		0x00
 #define     CONTEXT_CLAIM		0x04
 
-#define	PLIC_DISABLE_THRESHOLD		0xf
+#define	PLIC_DISABLE_THRESHOLD		0x7
 #define	PLIC_ENABLE_THRESHOLD		0
 
 struct plic_priv {