| Message ID | 20200521134544.816918-6-anup.patel@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Dedicated CLINT timer driver | expand |
On 5/21/20 9:45 AM, Anup Patel wrote: > We add DT bindings documentation for CLINT device. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > --- > .../bindings/timer/sifive,clint.txt | 33 +++++++++++++++++++ > 1 file changed, 33 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt > new file mode 100644 > index 000000000000..cae2dad1223a > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt > @@ -0,0 +1,33 @@ > +SiFive Core Local Interruptor (CLINT) > +------------------------------------- > + > +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core > +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts. > + > +It directly connects to the timer and inter-processor interrupt lines of > +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt > +controller is the parent interrupt controller for CLINT device. > + > +The clock frequency of CLINT is specified via "timebase-frequency" DT > +property of "/cpus" DT node. The "timebase-frequency" DT property is > +described in: Documentation/devicetree/bindings/riscv/cpus.yaml > + > +Required properties: > +- compatible : "sifive,clint-1.0.0" and a string identifying the actual > + detailed implementation in case that specific bugs need to be worked around. Should the "riscv,clint0" compatible string be documented here? This peripheral is not really specific to sifive, as it is present in most rocket-chip cores. > +- reg : Should contain 1 register range (address and length). > +- interrupts-extended : Specifies which HARTs (or CPUs) are connected to > + the CLINT. Each node pointed to should be a riscv,cpu-intc node, which > + has a riscv node as parent. > + > +Example: > + > + clint@2000000 { > + compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint"; > + interrupts-extended = < > + &cpu1-intc 3 &cpu1-intc 7 > + &cpu2-intc 3 &cpu2-intc 7 > + &cpu3-intc 3 &cpu3-intc 7 > + &cpu4-intc 3 &cpu4-intc 7>; > + reg = <0x2000000 0x4000000>; > + }; > --Sean
On Fri, May 22, 2020 at 1:35 AM Sean Anderson <seanga2@gmail.com> wrote: > > On 5/21/20 9:45 AM, Anup Patel wrote: > > We add DT bindings documentation for CLINT device. > > > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > > --- > > .../bindings/timer/sifive,clint.txt | 33 +++++++++++++++++++ > > 1 file changed, 33 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt > > > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt > > new file mode 100644 > > index 000000000000..cae2dad1223a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt > > @@ -0,0 +1,33 @@ > > +SiFive Core Local Interruptor (CLINT) > > +------------------------------------- > > + > > +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core > > +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts. > > + > > +It directly connects to the timer and inter-processor interrupt lines of > > +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt > > +controller is the parent interrupt controller for CLINT device. > > + > > +The clock frequency of CLINT is specified via "timebase-frequency" DT > > +property of "/cpus" DT node. The "timebase-frequency" DT property is > > +described in: Documentation/devicetree/bindings/riscv/cpus.yaml > > + > > +Required properties: > > +- compatible : "sifive,clint-1.0.0" and a string identifying the actual > > + detailed implementation in case that specific bugs need to be worked around. > > Should the "riscv,clint0" compatible string be documented here? This Yes, I forgot to add this compatible string. I will add in v2. > peripheral is not really specific to sifive, as it is present in most > rocket-chip cores. I agree that CLINT is present in a lot of non-SiFive RISC-V SOCs and FPGAs but this IP is only documented as part of SiFive FU540 SOC. (Refer, https://static.dev.sifive.com/FU540-C000-v1.0.pdf) The RISC-V foundation should host the CLINT spec independently under https://github.com/riscv and make CLINT spec totally open. For now, I have documented it just like PLIC DT bindings found at: Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt If RISC-V maintainers agree then I will document it as "RISC-V CLINT". @Palmer ?? @Paul ?? > > > +- reg : Should contain 1 register range (address and length). > > +- interrupts-extended : Specifies which HARTs (or CPUs) are connected to > > + the CLINT. Each node pointed to should be a riscv,cpu-intc node, which > > + has a riscv node as parent. > > + > > +Example: > > + > > + clint@2000000 { > > + compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint"; > > + interrupts-extended = < > > + &cpu1-intc 3 &cpu1-intc 7 > > + &cpu2-intc 3 &cpu2-intc 7 > > + &cpu3-intc 3 &cpu3-intc 7 > > + &cpu4-intc 3 &cpu4-intc 7>; > > + reg = <0x2000000 0x4000000>; > > + }; > > > > --Sean Regards, Anup
On 5/22/20 1:54 AM, Anup Patel wrote: > On Fri, May 22, 2020 at 1:35 AM Sean Anderson <seanga2@gmail.com> wrote: >> >> On 5/21/20 9:45 AM, Anup Patel wrote: >>> +Required properties: >>> +- compatible : "sifive,clint-1.0.0" and a string identifying the actual >>> + detailed implementation in case that specific bugs need to be worked around. >> >> Should the "riscv,clint0" compatible string be documented here? This > > Yes, I forgot to add this compatible string. I will add in v2. > >> peripheral is not really specific to sifive, as it is present in most >> rocket-chip cores. > > I agree that CLINT is present in a lot of non-SiFive RISC-V SOCs and > FPGAs but this IP is only documented as part of SiFive FU540 SOC. > (Refer, https://static.dev.sifive.com/FU540-C000-v1.0.pdf) > > The RISC-V foundation should host the CLINT spec independently > under https://github.com/riscv and make CLINT spec totally open. > > For now, I have documented it just like PLIC DT bindings found at: > Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt The PLIC seems to have its own RISC-V-sponsored documentation [1] which was split off from the older privileged specs. By your logic above, should it be renamed to riscv,plic0.txt (with a corresponding change in the documented compatible strings)? [1] https://github.com/riscv/riscv-plic-spec > > If RISC-V maintainers agree then I will document it as "RISC-V CLINT". > > @Palmer ?? @Paul ?? > > Regards, > Anup > --Sean
On Fri, May 22, 2020 at 11:59 AM Sean Anderson <seanga2@gmail.com> wrote: > > On 5/22/20 1:54 AM, Anup Patel wrote: > > On Fri, May 22, 2020 at 1:35 AM Sean Anderson <seanga2@gmail.com> wrote: > >> > >> On 5/21/20 9:45 AM, Anup Patel wrote: > >>> +Required properties: > >>> +- compatible : "sifive,clint-1.0.0" and a string identifying the actual > >>> + detailed implementation in case that specific bugs need to be worked around. > >> > >> Should the "riscv,clint0" compatible string be documented here? This > > > > Yes, I forgot to add this compatible string. I will add in v2. > > > >> peripheral is not really specific to sifive, as it is present in most > >> rocket-chip cores. > > > > I agree that CLINT is present in a lot of non-SiFive RISC-V SOCs and > > FPGAs but this IP is only documented as part of SiFive FU540 SOC. > > (Refer, https://static.dev.sifive.com/FU540-C000-v1.0.pdf) > > > > The RISC-V foundation should host the CLINT spec independently > > under https://github.com/riscv and make CLINT spec totally open. > > > > For now, I have documented it just like PLIC DT bindings found at: > > Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt > > The PLIC seems to have its own RISC-V-sponsored documentation [1] which > was split off from the older privileged specs. By your logic above, > should it be renamed to riscv,plic0.txt (with a corresponding change in > the documented compatible strings)? > > [1] https://github.com/riscv/riscv-plic-spec For PLIC bindings, we can certainly do the renaming because now we have PLIC v1 specification hosted on RISC-V Foundation Github. Regards, Anup
On Thu, 21 May 2020 23:29:36 PDT (-0700), seanga2@gmail.com wrote: > On 5/22/20 1:54 AM, Anup Patel wrote: >> On Fri, May 22, 2020 at 1:35 AM Sean Anderson <seanga2@gmail.com> wrote: >>> >>> On 5/21/20 9:45 AM, Anup Patel wrote: >>>> +Required properties: >>>> +- compatible : "sifive,clint-1.0.0" and a string identifying the actual >>>> + detailed implementation in case that specific bugs need to be worked around. >>> >>> Should the "riscv,clint0" compatible string be documented here? This >> >> Yes, I forgot to add this compatible string. I will add in v2. >> >>> peripheral is not really specific to sifive, as it is present in most >>> rocket-chip cores. >> >> I agree that CLINT is present in a lot of non-SiFive RISC-V SOCs and >> FPGAs but this IP is only documented as part of SiFive FU540 SOC. >> (Refer, https://static.dev.sifive.com/FU540-C000-v1.0.pdf) >> >> The RISC-V foundation should host the CLINT spec independently >> under https://github.com/riscv and make CLINT spec totally open. >> >> For now, I have documented it just like PLIC DT bindings found at: >> Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt > > The PLIC seems to have its own RISC-V-sponsored documentation [1] which > was split off from the older privileged specs. By your logic above, > should it be renamed to riscv,plic0.txt (with a corresponding change in > the documented compatible strings)? > > [1] https://github.com/riscv/riscv-plic-spec Let's propose tagging that PLIC spec as v1.0.0 in the platform spec group, but I don't see a reason why that wouldn't be viable. Assuming that's all OK, we can start calling this a RISC-V PLIC (in addition to a SiFive PLIC, as they'll be compatible). >> >> If RISC-V maintainers agree then I will document it as "RISC-V CLINT". >> >> @Palmer ?? @Paul ?? The CLINT is a SiFive spec. It has open source RTL so it's been implemented in other designs, but it's not a RISC-V spec. The CLIC, which is a superset of the CLINT, is a RISC-V spec. IIRC it's not finished yet (it's the fast interrupts task group), but presumably we should have a "riscv,clic-2.0.0" (or whatever it ends up being called) compat string to go along with the specification. >> Regards, >> Anup >> > > --Sean
On 5/26/20 8:32 PM, Palmer Dabbelt wrote: > On Thu, 21 May 2020 23:29:36 PDT (-0700), seanga2@gmail.com wrote: >> On 5/22/20 1:54 AM, Anup Patel wrote: >>> On Fri, May 22, 2020 at 1:35 AM Sean Anderson <seanga2@gmail.com> wrote: >>>> >>>> On 5/21/20 9:45 AM, Anup Patel wrote: >>>>> +Required properties: >>>>> +- compatible : "sifive,clint-1.0.0" and a string identifying the actual >>>>> + detailed implementation in case that specific bugs need to be worked around. >>>> >>>> Should the "riscv,clint0" compatible string be documented here? This >>> >>> Yes, I forgot to add this compatible string. I will add in v2. >>> >>>> peripheral is not really specific to sifive, as it is present in most >>>> rocket-chip cores. >>> >>> I agree that CLINT is present in a lot of non-SiFive RISC-V SOCs and >>> FPGAs but this IP is only documented as part of SiFive FU540 SOC. >>> (Refer, https://static.dev.sifive.com/FU540-C000-v1.0.pdf) >>> >>> The RISC-V foundation should host the CLINT spec independently >>> under https://github.com/riscv and make CLINT spec totally open. >>> >>> For now, I have documented it just like PLIC DT bindings found at: >>> Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt >> >> The PLIC seems to have its own RISC-V-sponsored documentation [1] which >> was split off from the older privileged specs. By your logic above, >> should it be renamed to riscv,plic0.txt (with a corresponding change in >> the documented compatible strings)? >> >> [1] https://github.com/riscv/riscv-plic-spec > > Let's propose tagging that PLIC spec as v1.0.0 in the platform spec group, but > I don't see a reason why that wouldn't be viable. Assuming that's all OK, we > can start calling this a RISC-V PLIC (in addition to a SiFive PLIC, as they'll > be compatible). Is there a version anyewhere in that spec? I looked around a bit and couldn't find one. >>> >>> If RISC-V maintainers agree then I will document it as "RISC-V CLINT". >>> >>> @Palmer ?? @Paul ?? > > The CLINT is a SiFive spec. It has open source RTL so it's been implemented in > other designs, but it's not a RISC-V spec. The CLIC, which is a superset of > the CLINT, is a RISC-V spec. IIRC it's not finished yet (it's the fast > interrupts task group), but presumably we should have a "riscv,clic-2.0.0" (or > whatever it ends up being called) compat string to go along with the > specification. The rocket chip is a Chips Alliance project on github; presumably the "proper" compatibility string would be something like "chips-alliance,clint"? Alternatively, it is already referred to as "riscv,clint0" in U-Boot, following the pattern of the plic. --Sean
On Tue, May 26, 2020 at 05:32:30PM -0700, Palmer Dabbelt wrote: > On Thu, 21 May 2020 23:29:36 PDT (-0700), seanga2@gmail.com wrote: > > On 5/22/20 1:54 AM, Anup Patel wrote: > > > On Fri, May 22, 2020 at 1:35 AM Sean Anderson <seanga2@gmail.com> wrote: > > > > > > > > On 5/21/20 9:45 AM, Anup Patel wrote: > > > > > +Required properties: > > > > > +- compatible : "sifive,clint-1.0.0" and a string identifying the actual > > > > > + detailed implementation in case that specific bugs need to be worked around. > > > > > > > > Should the "riscv,clint0" compatible string be documented here? This > > > > > > Yes, I forgot to add this compatible string. I will add in v2. > > > > > > > peripheral is not really specific to sifive, as it is present in most > > > > rocket-chip cores. > > > > > > I agree that CLINT is present in a lot of non-SiFive RISC-V SOCs and > > > FPGAs but this IP is only documented as part of SiFive FU540 SOC. > > > (Refer, https://static.dev.sifive.com/FU540-C000-v1.0.pdf) > > > > > > The RISC-V foundation should host the CLINT spec independently > > > under https://github.com/riscv and make CLINT spec totally open. > > > > > > For now, I have documented it just like PLIC DT bindings found at: > > > Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt > > > > The PLIC seems to have its own RISC-V-sponsored documentation [1] which > > was split off from the older privileged specs. By your logic above, > > should it be renamed to riscv,plic0.txt (with a corresponding change in > > the documented compatible strings)? > > > > [1] https://github.com/riscv/riscv-plic-spec > > Let's propose tagging that PLIC spec as v1.0.0 in the platform spec group, but > I don't see a reason why that wouldn't be viable. Assuming that's all OK, we > can start calling this a RISC-V PLIC (in addition to a SiFive PLIC, as they'll > be compatible). > > > > > > > If RISC-V maintainers agree then I will document it as "RISC-V CLINT". > > > > > > @Palmer ?? @Paul ?? > > The CLINT is a SiFive spec. It has open source RTL so it's been implemented in > other designs, but it's not a RISC-V spec. The CLIC, which is a superset of > the CLINT, is a RISC-V spec. IIRC it's not finished yet (it's the fast > interrupts task group), but presumably we should have a "riscv,clic-2.0.0" (or > whatever it ends up being called) compat string to go along with the > specification. Whatever you all decide on, note that "sifive,<block><num>" is a SiFive thing (as it is documented) and <num> corresponds to tag of the IP implmentation (at least it is supposed to). So you can't just copy that with 'riscv,<block><num>' unless you have the same IP versioning and update the documentation. Using a spec version is fine, but not standalone. You need implementation specific compatible too because no one perfectly implements any spec and/or there details a spec may not cover. Rob
On Thu, 21 May 2020 06:45:44 PDT (-0700), Anup Patel wrote: > We add DT bindings documentation for CLINT device. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > --- > .../bindings/timer/sifive,clint.txt | 33 +++++++++++++++++++ > 1 file changed, 33 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt > new file mode 100644 > index 000000000000..cae2dad1223a > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt > @@ -0,0 +1,33 @@ > +SiFive Core Local Interruptor (CLINT) > +------------------------------------- > + > +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core > +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts. > + > +It directly connects to the timer and inter-processor interrupt lines of > +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt > +controller is the parent interrupt controller for CLINT device. > + > +The clock frequency of CLINT is specified via "timebase-frequency" DT > +property of "/cpus" DT node. The "timebase-frequency" DT property is > +described in: Documentation/devicetree/bindings/riscv/cpus.yaml > + > +Required properties: > +- compatible : "sifive,clint-1.0.0" and a string identifying the actual > + detailed implementation in case that specific bugs need to be worked around. > +- reg : Should contain 1 register range (address and length). > +- interrupts-extended : Specifies which HARTs (or CPUs) are connected to > + the CLINT. Each node pointed to should be a riscv,cpu-intc node, which > + has a riscv node as parent. > + > +Example: > + > + clint@2000000 { > + compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint"; > + interrupts-extended = < > + &cpu1-intc 3 &cpu1-intc 7 > + &cpu2-intc 3 &cpu2-intc 7 > + &cpu3-intc 3 &cpu3-intc 7 > + &cpu4-intc 3 &cpu4-intc 7>; > + reg = <0x2000000 0x4000000>; > + }; Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt new file mode 100644 index 000000000000..cae2dad1223a --- /dev/null +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt @@ -0,0 +1,33 @@ +SiFive Core Local Interruptor (CLINT) +------------------------------------- + +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts. + +It directly connects to the timer and inter-processor interrupt lines of +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt +controller is the parent interrupt controller for CLINT device. + +The clock frequency of CLINT is specified via "timebase-frequency" DT +property of "/cpus" DT node. The "timebase-frequency" DT property is +described in: Documentation/devicetree/bindings/riscv/cpus.yaml + +Required properties: +- compatible : "sifive,clint-1.0.0" and a string identifying the actual + detailed implementation in case that specific bugs need to be worked around. +- reg : Should contain 1 register range (address and length). +- interrupts-extended : Specifies which HARTs (or CPUs) are connected to + the CLINT. Each node pointed to should be a riscv,cpu-intc node, which + has a riscv node as parent. + +Example: + + clint@2000000 { + compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint"; + interrupts-extended = < + &cpu1-intc 3 &cpu1-intc 7 + &cpu2-intc 3 &cpu2-intc 7 + &cpu3-intc 3 &cpu3-intc 7 + &cpu4-intc 3 &cpu4-intc 7>; + reg = <0x2000000 0x4000000>; + };
We add DT bindings documentation for CLINT device. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- .../bindings/timer/sifive,clint.txt | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt