mbox series

[v2,0/2] enable spi flash and update is25wp256d page write capabilities

Message ID 1589885187-31247-1-git-send-email-sagar.kadam@sifive.com (mailing list archive)
Headers show
Series enable spi flash and update is25wp256d page write capabilities | expand

Message

Sagar Shrikant Kadam May 19, 2020, 10:46 a.m. UTC
HiFive Unleashed A00 board has is25wp256d snor chip. It is observed
that it gets configured with Serial Input Page program by the end
of spi_nor_scan. Using the post bfpt fixup hook we prioritize the
page program settings to use quad input page program (opcode:0x34)
over serial input page program (opcode: 0x12).

The patchset is tested on Linux 5.7.0-rc5.

Changelog:
===============================
V2:
-Split common code between is25lp256 and is25wp256 devices as suggested
 Added a generic post bfpt fixup handler that identifies the flash parts
 based on their device id and uses the corresponding fixup. Other device's
 that need a post bfpt fixup can just add the device id check and either
 reuse the available fixups or write the necessary fixup code if one is not
 available.
 
V1:
-Moved SPI_SIFIVE from defconfig to Kconfig.socs for SOC_SIFIVE.
 Retained it's configurability using "imply" instead of "select"

V0: Base version patch (Tested on 5.7.0-rc3).


Sagar Shrikant Kadam (2):
  riscv: defconfig: enable spi nor on Hifive Unleashed A00
  spi: nor: update page program settings for is25wp256 using post bfpt
    fixup

 arch/riscv/Kconfig.socs      |  1 +
 arch/riscv/configs/defconfig |  3 +-
 drivers/mtd/spi-nor/issi.c   | 72 ++++++++++++++++++++++++++++++++++++--------
 3 files changed, 63 insertions(+), 13 deletions(-)

Comments

Sagar Shrikant Kadam May 25, 2020, 5:45 a.m. UTC | #1
Hi,

A gentle reminder.
Any suggestions here?

BR,
Sagar Kadam

> -----Original Message-----
> From: Sagar Kadam <sagar.kadam@sifive.com>
> Sent: Tuesday, May 19, 2020 4:16 PM
> To: linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> mtd@lists.infradead.org
> Cc: Paul Walmsley <paul.walmsley@sifive.com>; palmer@dabbelt.com;
> aou@eecs.berkeley.edu; tudor.ambarus@microchip.com;
> miquel.raynal@bootlin.com; richard@nod.at; vigneshr@ti.com;
> anup.patel@wdc.com; Sagar Kadam <sagar.kadam@sifive.com>
> Subject: [PATCH v2 0/2] enable spi flash and update is25wp256d page write
> capabilities
> 
> HiFive Unleashed A00 board has is25wp256d snor chip. It is observed that it
> gets configured with Serial Input Page program by the end of spi_nor_scan.
> Using the post bfpt fixup hook we prioritize the page program settings to
> use quad input page program (opcode:0x34) over serial input page program
> (opcode: 0x12).
> 
> The patchset is tested on Linux 5.7.0-rc5.
> 
> Changelog:
> ===============================
> V2:
> -Split common code between is25lp256 and is25wp256 devices as suggested
> Added a generic post bfpt fixup handler that identifies the flash parts
> based on their device id and uses the corresponding fixup. Other device's
> that need a post bfpt fixup can just add the device id check and either
> reuse the available fixups or write the necessary fixup code if one is not
> available.
> 
> V1:
> -Moved SPI_SIFIVE from defconfig to Kconfig.socs for SOC_SIFIVE.
>  Retained it's configurability using "imply" instead of "select"
> 
> V0: Base version patch (Tested on 5.7.0-rc3).
> 
> 
> Sagar Shrikant Kadam (2):
>   riscv: defconfig: enable spi nor on Hifive Unleashed A00
>   spi: nor: update page program settings for is25wp256 using post bfpt
>     fixup
> 
>  arch/riscv/Kconfig.socs      |  1 +
>  arch/riscv/configs/defconfig |  3 +-
>  drivers/mtd/spi-nor/issi.c   | 72
> ++++++++++++++++++++++++++++++++++++--------
>  3 files changed, 63 insertions(+), 13 deletions(-)
> 
> --
> 2.7.4