diff mbox series

ARM: dts: meson: Align L2 cache-controller nodename with dtschema

Message ID 20200626080626.4080-1-krzk@kernel.org (mailing list archive)
State Mainlined
Commit 54320dcaa2522db3222c02d68b52cfed32a2e95b
Headers show
Series ARM: dts: meson: Align L2 cache-controller nodename with dtschema | expand

Commit Message

Krzysztof Kozlowski June 26, 2020, 8:06 a.m. UTC
Fix dtschema validator warnings like:
     l2-cache-controller@c4200000: $nodename:0:
         'l2-cache-controller@c4200000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/meson.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Martin Blumenstingl June 26, 2020, 8:31 p.m. UTC | #1
Hi Krzysztof,

thank you for this patch!

On Fri, Jun 26, 2020 at 1:59 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> Fix dtschema validator warnings like:
>      l2-cache-controller@c4200000: $nodename:0:
>          'l2-cache-controller@c4200000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>


Best regards,
Martin
Kevin Hilman June 29, 2020, 11:19 p.m. UTC | #2
On Fri, 26 Jun 2020 10:06:26 +0200, Krzysztof Kozlowski wrote:
> Fix dtschema validator warnings like:
>      l2-cache-controller@c4200000: $nodename:0:
>          'l2-cache-controller@c4200000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

Applied, thanks!

[1/1] ARM: dts: meson: Align L2 cache-controller nodename with dtschema
      commit: 54320dcaa2522db3222c02d68b52cfed32a2e95b

Best regards,
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index ae89deaa8c9c..91129dc70d83 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -11,7 +11,7 @@ 
 	#size-cells = <1>;
 	interrupt-parent = <&gic>;
 
-	L2: l2-cache-controller@c4200000 {
+	L2: cache-controller@c4200000 {
 		compatible = "arm,pl310-cache";
 		reg = <0xc4200000 0x1000>;
 		cache-unified;