| Message ID | 20200814173037.17822-4-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | Add PCIe EP nodes on RZ/G2[EMN] | expand |
Hello! On 14.08.2020 20:30, Lad Prabhakar wrote: > Add PCIe EP nodes to R8A774A1 (RZ/G2M) SoC dtsi. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi > index a603d947970e..50e9ed16a36d 100644 > --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi > @@ -2369,6 +2369,44 @@ > status = "disabled"; > }; > > + pciec0_ep: pcie_ep@fe000000 { Hyphens are preferred over underscores in the node/prop names. [...]> + pciec1_ep: pcie_ep@ee800000 { Ditto, should be "pci-ep@ee800000". [...] MBR, Sergei
Hi Sergei, Thank you for the review. On Sat, Aug 15, 2020 at 9:45 AM Sergei Shtylyov <sergei.shtylyov@gmail.com> wrote: > > Hello! > > On 14.08.2020 20:30, Lad Prabhakar wrote: > > > Add PCIe EP nodes to R8A774A1 (RZ/G2M) SoC dtsi. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++++++ > > 1 file changed, 38 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi > > index a603d947970e..50e9ed16a36d 100644 > > --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi > > @@ -2369,6 +2369,44 @@ > > status = "disabled"; > > }; > > > > + pciec0_ep: pcie_ep@fe000000 { > > Hyphens are preferred over underscores in the node/prop names. > > [...]> + pciec1_ep: pcie_ep@ee800000 { > > Ditto, should be "pci-ep@ee800000". > My bad will fix that in v2. Cheers, Prabhakar > [...] > > MBR, Sergei
On 18.08.2020 10:23, Lad, Prabhakar wrote: [...] >>> Add PCIe EP nodes to R8A774A1 (RZ/G2M) SoC dtsi. >>> >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> >>> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> >>> --- >>> arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++++++ >>> 1 file changed, 38 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi >>> index a603d947970e..50e9ed16a36d 100644 >>> --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi >>> +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi >>> @@ -2369,6 +2369,44 @@ >>> status = "disabled"; >>> }; >>> >>> + pciec0_ep: pcie_ep@fe000000 { >> >> Hyphens are preferred over underscores in the node/prop names. >> >> [...] >> + pciec1_ep: pcie_ep@ee800000 { >> >> Ditto, should be "pci-ep@ee800000". >> > My bad will fix that in v2. Sorry, I meant to type "pcie-ep@ee800000". > Cheers, > Prabhakar MBR, Sergei
On Fri, Aug 14, 2020 at 7:33 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add PCIe EP nodes to R8A774A1 (RZ/G2M) SoC dtsi. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.10, with s/pcie_ep@/pcie-ep@/. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index a603d947970e..50e9ed16a36d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2369,6 +2369,44 @@ status = "disabled"; }; + pciec0_ep: pcie_ep@fe000000 { + compatible = "renesas,r8a774a1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xfe000000 0 0x80000>, + <0x0 0xfe100000 0 0x100000>, + <0x0 0xfe200000 0 0x200000>, + <0x0 0x30000000 0 0x8000000>, + <0x0 0x38000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + resets = <&cpg 319>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pciec1_ep: pcie_ep@ee800000 { + compatible = "renesas,r8a774a1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xee800000 0 0x80000>, + <0x0 0xee900000 0 0x100000>, + <0x0 0xeea00000 0 0x200000>, + <0x0 0xc0000000 0 0x8000000>, + <0x0 0xc8000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>; + clock-names = "pcie"; + resets = <&cpg 318>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + status = "disabled"; + }; + fdp1@fe940000 { compatible = "renesas,fdp1"; reg = <0 0xfe940000 0 0x2400>;