| Message ID | 20200824190701.8447-4-krzk@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/16] dt-bindings: mfd: rohm, bd71847-pmic: Correct clock properties requirements | expand |
Hi Krzysztof, On Mon, Aug 24, 2020 at 4:07 PM Krzysztof Kozlowski <krzk@kernel.org> wrote: > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi > index bf0859f1e1fa..5b5af8b381df 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi > @@ -70,7 +70,7 @@ > &ecspi2 { > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_espi2>; > - cs-gpios = <&gpio5 9 0>; > + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; I have already sent a patch fixing this: https://www.spinics.net/lists/arm-kernel/msg830895.html
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index bf0859f1e1fa..5b5af8b381df 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -70,7 +70,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_espi2>; - cs-gpios = <&gpio5 9 0>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; status = "okay"; eeprom@0 {
Since the "spi-cs-high" property is not present, the SPI chip select pin polarity is active low. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> --- arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)