Message ID | 1602609110-11504-2-git-send-email-tdas@codeaurora.org (mailing list archive) |
---|---|
State | Changes Requested, archived |
Headers | show |
Series | Add Camera clock controller driver for SC7180 | expand |
Quoting Taniya Das (2020-10-13 10:11:48) > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > index 26139ef..17e1fc0 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.c > +++ b/drivers/clk/qcom/clk-alpha-pll.c > @@ -1561,3 +1571,73 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { > .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, > }; > EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); > + > +void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, > + const struct alpha_pll_config *config) > +{ > + if (config->l) > + regmap_write(regmap, PLL_L_VAL(pll), config->l); Maybe make a helper function for this too. That way we can't mix up the if condition with the value in the write. clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, unsigned int val) { if (val) regmap_write(regmap, reg, val); } and how are we so lucky that zero isn't a value that we may need to write? > + > + if (config->alpha) > + regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); > + > + if (config->user_ctl_val) > + regmap_write(regmap, PLL_USER_CTL(pll), config->user_ctl_val); > + > + if (config->config_ctl_val) > + regmap_write(regmap, PLL_CONFIG_CTL(pll), > + config->config_ctl_val); > + > + if (config->config_ctl_hi_val) > + regmap_write(regmap, PLL_CONFIG_CTL_U(pll), > + config->config_ctl_hi_val); > + > + if (config->test_ctl_val) > + regmap_write(regmap, PLL_TEST_CTL(pll), > + config->test_ctl_val); > + > + if (config->test_ctl_hi_val) > + regmap_write(regmap, PLL_TEST_CTL_U(pll), > + config->test_ctl_hi_val); > +} > +EXPORT_SYMBOL_GPL(clk_agera_pll_configure); > + > +static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long prate) > +{ > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); > + u32 l, alpha_width = pll_alpha_width(pll); > + unsigned long rrate, max = rate + PLL_RATE_MARGIN; > + u64 a; > + > + rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); > + > + /* > + * Due to limited number of bits for fractional rate programming, the > + * rounded up rate could be marginally higher than the requested rate. > + */ > + if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) { > + pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", > + clk_hw_get_name(hw), rrate, rate, max); > + return -EINVAL; > + } Can this be extracted into a helper function? > + > + /* change L_VAL without having to go through the power on sequence */ > + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); > + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); > + > + if (clk_hw_is_enabled(hw)) > + return wait_for_pll_enable_lock(pll); > + > + return 0; > +} > +
Thanks Stephen for the review comments. On 10/14/2020 7:37 AM, Stephen Boyd wrote: > Quoting Taniya Das (2020-10-13 10:11:48) >> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c >> index 26139ef..17e1fc0 100644 >> --- a/drivers/clk/qcom/clk-alpha-pll.c >> +++ b/drivers/clk/qcom/clk-alpha-pll.c >> @@ -1561,3 +1571,73 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { >> .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, >> }; >> EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); >> + >> +void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, >> + const struct alpha_pll_config *config) >> +{ >> + if (config->l) >> + regmap_write(regmap, PLL_L_VAL(pll), config->l); > > Maybe make a helper function for this too. That way we can't mix up the > if condition with the value in the write. > Sure, I will add a helper function. > clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); > > static void clk_alpha_pll_write_config(struct regmap *regmap, > unsigned int reg, > unsigned int val) { > if (val) > regmap_write(regmap, reg, val); > } > > and how are we so lucky that zero isn't a value that we may need to > write? > >> + >> + if (config->alpha) >> + regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); >> + >> + if (config->user_ctl_val) >> + regmap_write(regmap, PLL_USER_CTL(pll), config->user_ctl_val); >> + >> + if (config->config_ctl_val) >> + regmap_write(regmap, PLL_CONFIG_CTL(pll), >> + config->config_ctl_val); >> + >> + if (config->config_ctl_hi_val) >> + regmap_write(regmap, PLL_CONFIG_CTL_U(pll), >> + config->config_ctl_hi_val); >> + >> + if (config->test_ctl_val) >> + regmap_write(regmap, PLL_TEST_CTL(pll), >> + config->test_ctl_val); >> + >> + if (config->test_ctl_hi_val) >> + regmap_write(regmap, PLL_TEST_CTL_U(pll), >> + config->test_ctl_hi_val); >> +} >> +EXPORT_SYMBOL_GPL(clk_agera_pll_configure); >> + >> +static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, >> + unsigned long prate) >> +{ >> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); >> + u32 l, alpha_width = pll_alpha_width(pll); >> + unsigned long rrate, max = rate + PLL_RATE_MARGIN; >> + u64 a; >> + >> + rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); >> + >> + /* >> + * Due to limited number of bits for fractional rate programming, the >> + * rounded up rate could be marginally higher than the requested rate. >> + */ >> + if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) { >> + pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", >> + clk_hw_get_name(hw), rrate, rate, max); >> + return -EINVAL; >> + } > > Can this be extracted into a helper function? > Yes, I will add this too. >> + >> + /* change L_VAL without having to go through the power on sequence */ >> + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); >> + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); >> + >> + if (clk_hw_is_enabled(hw)) >> + return wait_for_pll_enable_lock(pll); >> + >> + return 0; >> +} >> +
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 26139ef..17e1fc0 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -116,6 +116,16 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_OPMODE] = 0x38, [PLL_OFF_ALPHA_VAL] = 0x40, }, + [CLK_ALPHA_PLL_TYPE_AGERA] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_USER_CTL] = 0x0c, + [PLL_OFF_CONFIG_CTL] = 0x10, + [PLL_OFF_CONFIG_CTL_U] = 0x14, + [PLL_OFF_TEST_CTL] = 0x18, + [PLL_OFF_TEST_CTL_U] = 0x1c, + [PLL_OFF_STATUS] = 0x2c, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); @@ -1561,3 +1571,73 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); + +void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) +{ + if (config->l) + regmap_write(regmap, PLL_L_VAL(pll), config->l); + + if (config->alpha) + regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); + + if (config->user_ctl_val) + regmap_write(regmap, PLL_USER_CTL(pll), config->user_ctl_val); + + if (config->config_ctl_val) + regmap_write(regmap, PLL_CONFIG_CTL(pll), + config->config_ctl_val); + + if (config->config_ctl_hi_val) + regmap_write(regmap, PLL_CONFIG_CTL_U(pll), + config->config_ctl_hi_val); + + if (config->test_ctl_val) + regmap_write(regmap, PLL_TEST_CTL(pll), + config->test_ctl_val); + + if (config->test_ctl_hi_val) + regmap_write(regmap, PLL_TEST_CTL_U(pll), + config->test_ctl_hi_val); +} +EXPORT_SYMBOL_GPL(clk_agera_pll_configure); + +static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 l, alpha_width = pll_alpha_width(pll); + unsigned long rrate, max = rate + PLL_RATE_MARGIN; + u64 a; + + rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); + + /* + * Due to limited number of bits for fractional rate programming, the + * rounded up rate could be marginally higher than the requested rate. + */ + if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) { + pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", + clk_hw_get_name(hw), rrate, rate, max); + return -EINVAL; + } + + /* change L_VAL without having to go through the power on sequence */ + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); + + if (clk_hw_is_enabled(hw)) + return wait_for_pll_enable_lock(pll); + + return 0; +} + +const struct clk_ops clk_alpha_pll_agera_ops = { + .enable = clk_alpha_pll_enable, + .disable = clk_alpha_pll_disable, + .is_enabled = clk_alpha_pll_is_enabled, + .recalc_rate = alpha_pll_fabia_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, + .set_rate = clk_alpha_pll_agera_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index d3201b8..0ea30d2 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -15,6 +15,7 @@ enum { CLK_ALPHA_PLL_TYPE_FABIA, CLK_ALPHA_PLL_TYPE_TRION, CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, + CLK_ALPHA_PLL_TYPE_AGERA, CLK_ALPHA_PLL_TYPE_MAX, }; @@ -141,6 +142,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops; extern const struct clk_ops clk_alpha_pll_lucid_ops; #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; +extern const struct clk_ops clk_alpha_pll_agera_ops; void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); @@ -148,6 +150,8 @@ void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); +void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); #define clk_lucid_pll_configure(pll, regmap, config) \ clk_trion_pll_configure(pll, regmap, config)
Add programming sequence support for managing the Agera PLLs. Signed-off-by: Taniya Das <tdas@codeaurora.org> --- drivers/clk/qcom/clk-alpha-pll.c | 80 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 4 ++ 2 files changed, 84 insertions(+) -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.