| Message ID | 20201027141740.18336-5-bmeng.cn@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box | expand |
On Tue, Oct 27, 2020 at 7:52 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > Previously IOSCB_CFG was created as an unimplemented device. With > the new IOSCB model, its memory range is already covered by the > IOSCB hence remove the previous unimplemented device creation in > the SoC codes. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > --- > > hw/riscv/Kconfig | 1 + > hw/riscv/microchip_pfsoc.c | 13 ++++++++----- > include/hw/riscv/microchip_pfsoc.h | 4 +++- > 3 files changed, 12 insertions(+), 6 deletions(-) > > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig > index c8e50bde99..8f043e38e0 100644 > --- a/hw/riscv/Kconfig > +++ b/hw/riscv/Kconfig > @@ -5,6 +5,7 @@ config MICROCHIP_PFSOC > bool > select CADENCE_SDHCI > select MCHP_PFSOC_DMC > + select MCHP_PFSOC_IOSCB > select MCHP_PFSOC_MMUART > select MSI_NONBROKEN > select SIFIVE_CLINT > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index 85be2bcde8..05fb5004a1 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -16,6 +16,7 @@ > * 5) SiFive Platform DMA (Direct Memory Access Controller) > * 6) GEM (Gigabit Ethernet MAC Controller) > * 7) DMC (DDR Memory Controller) > + * 8) IOSCB modules > * > * This board currently generates devicetree dynamically that indicates at least > * two harts and up to five harts. > @@ -100,7 +101,7 @@ static const struct MemmapEntry { > [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, > [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, > [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, > - [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, > + [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, This one matches the docs! :) Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, > }; > > @@ -144,6 +145,8 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) > > object_initialize_child(obj, "sd-controller", &s->sdhci, > TYPE_CADENCE_SDHCI); > + > + object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); > } > > static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) > @@ -355,10 +358,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) > memmap[MICROCHIP_PFSOC_ENVM_DATA].base, > envm_data); > > - /* IOSCBCFG */ > - create_unimplemented_device("microchip.pfsoc.ioscb.cfg", > - memmap[MICROCHIP_PFSOC_IOSCB_CFG].base, > - memmap[MICROCHIP_PFSOC_IOSCB_CFG].size); > + /* IOSCB */ > + sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, > + memmap[MICROCHIP_PFSOC_IOSCB].base); > } > > static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) > diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h > index 5b81e26241..a244ae6d39 100644 > --- a/include/hw/riscv/microchip_pfsoc.h > +++ b/include/hw/riscv/microchip_pfsoc.h > @@ -25,6 +25,7 @@ > #include "hw/char/mchp_pfsoc_mmuart.h" > #include "hw/dma/sifive_pdma.h" > #include "hw/misc/mchp_pfsoc_dmc.h" > +#include "hw/misc/mchp_pfsoc_ioscb.h" > #include "hw/net/cadence_gem.h" > #include "hw/sd/cadence_sdhci.h" > > @@ -40,6 +41,7 @@ typedef struct MicrochipPFSoCState { > DeviceState *plic; > MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; > MchpPfSoCDdrCfgState ddr_cfg; > + MchpPfSoCIoscbState ioscb; > MchpPfSoCMMUartState *serial0; > MchpPfSoCMMUartState *serial1; > MchpPfSoCMMUartState *serial2; > @@ -99,7 +101,7 @@ enum { > MICROCHIP_PFSOC_GPIO2, > MICROCHIP_PFSOC_ENVM_CFG, > MICROCHIP_PFSOC_ENVM_DATA, > - MICROCHIP_PFSOC_IOSCB_CFG, > + MICROCHIP_PFSOC_IOSCB, > MICROCHIP_PFSOC_DRAM, > }; > > -- > 2.25.1 > >
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index c8e50bde99..8f043e38e0 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -5,6 +5,7 @@ config MICROCHIP_PFSOC bool select CADENCE_SDHCI select MCHP_PFSOC_DMC + select MCHP_PFSOC_IOSCB select MCHP_PFSOC_MMUART select MSI_NONBROKEN select SIFIVE_CLINT diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 85be2bcde8..05fb5004a1 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -16,6 +16,7 @@ * 5) SiFive Platform DMA (Direct Memory Access Controller) * 6) GEM (Gigabit Ethernet MAC Controller) * 7) DMC (DDR Memory Controller) + * 8) IOSCB modules * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -100,7 +101,7 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, - [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, + [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, }; @@ -144,6 +145,8 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) object_initialize_child(obj, "sd-controller", &s->sdhci, TYPE_CADENCE_SDHCI); + + object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); } static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) @@ -355,10 +358,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) memmap[MICROCHIP_PFSOC_ENVM_DATA].base, envm_data); - /* IOSCBCFG */ - create_unimplemented_device("microchip.pfsoc.ioscb.cfg", - memmap[MICROCHIP_PFSOC_IOSCB_CFG].base, - memmap[MICROCHIP_PFSOC_IOSCB_CFG].size); + /* IOSCB */ + sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, + memmap[MICROCHIP_PFSOC_IOSCB].base); } static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 5b81e26241..a244ae6d39 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -25,6 +25,7 @@ #include "hw/char/mchp_pfsoc_mmuart.h" #include "hw/dma/sifive_pdma.h" #include "hw/misc/mchp_pfsoc_dmc.h" +#include "hw/misc/mchp_pfsoc_ioscb.h" #include "hw/net/cadence_gem.h" #include "hw/sd/cadence_sdhci.h" @@ -40,6 +41,7 @@ typedef struct MicrochipPFSoCState { DeviceState *plic; MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; MchpPfSoCDdrCfgState ddr_cfg; + MchpPfSoCIoscbState ioscb; MchpPfSoCMMUartState *serial0; MchpPfSoCMMUartState *serial1; MchpPfSoCMMUartState *serial2; @@ -99,7 +101,7 @@ enum { MICROCHIP_PFSOC_GPIO2, MICROCHIP_PFSOC_ENVM_CFG, MICROCHIP_PFSOC_ENVM_DATA, - MICROCHIP_PFSOC_IOSCB_CFG, + MICROCHIP_PFSOC_IOSCB, MICROCHIP_PFSOC_DRAM, };