| Message ID | 20201201134330.3037007-2-daniel@0x0f.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 80e73332ee829cd55d86272b7d3d4d5f0fc4c4ff |
| Headers | show |
| Series | ARM: mstar: Add basic support for i2m and SMP | expand |
On Tue, Dec 01, 2020 at 10:43:21PM +0900, Daniel Palmer wrote: > This adds a YAML description of the smpctrl node needed by the > platform code for the MStar/SigmaStar Armv7 SoCs to boot secondary cpus. You need an 'enable-method' string defined too. > > Signed-off-by: Daniel Palmer <daniel@0x0f.com> > --- > .../bindings/arm/mstar/mstar,smpctrl.yaml | 40 +++++++++++++++++++ > 1 file changed, 40 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml > > diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml > new file mode 100644 > index 000000000000..599c65980f5d > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml > @@ -0,0 +1,40 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright 2020 thingy.jp. > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: MStar/SigmaStar Armv7 SoC SMP control registers > + > +maintainers: > + - Daniel Palmer <daniel@thingy.jp> > + > +description: | > + MStar/SigmaStar's Armv7 SoCs that have more than one processor > + have a region of registers that allow setting the boot address > + and a magic number that allows secondary processors to leave > + the loop they are parked in by the boot ROM. > + > +properties: > + compatible: > + items: > + - enum: > + - sstar,ssd201-smpctrl # SSD201/SSD202D > + - const: mstar,smpctrl > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + smpctrl@204000 { > + compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl"; > + reg = <0x204000 0x200>; > + }; > -- > 2.29.2 >
On Wed, Dec 9, 2020 at 5:35 PM Rob Herring <robh@kernel.org> wrote: > > On Tue, Dec 01, 2020 at 10:43:21PM +0900, Daniel Palmer wrote: > > This adds a YAML description of the smpctrl node needed by the > > platform code for the MStar/SigmaStar Armv7 SoCs to boot secondary cpus. > > You need an 'enable-method' string defined too. I had already applied the series by the time I saw this reply. Daniel, please send patches on top of this series to address Rob's comments. Arnd
Hi Rob, On Thu, 10 Dec 2020 at 01:35, Rob Herring <robh@kernel.org> wrote: > On Tue, Dec 01, 2020 at 10:43:21PM +0900, Daniel Palmer wrote: > > This adds a YAML description of the smpctrl node needed by the > > platform code for the MStar/SigmaStar Armv7 SoCs to boot secondary cpus. > > You need an 'enable-method' string defined too. The machine has smp ops set so I didn't think this was needed? I was going to convert it to using enable-method in the cpu node but the same code is used to enable the secondary cpu in all of the chips with a second cpu so I didn't think I was really needed. Thanks, Daniel
Hi Arnd, On Thu, 10 Dec 2020 at 02:45, Arnd Bergmann <arnd@kernel.org> wrote: > Daniel, please send patches on top of this series to address Rob's > comments. Will do. On the enabled method one I had a question for Rob so I'll wait for a reply to that and then send the fixes. Sorry about the trouble caused. Thanks, Daniel
diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml new file mode 100644 index 000000000000..599c65980f5d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 thingy.jp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MStar/SigmaStar Armv7 SoC SMP control registers + +maintainers: + - Daniel Palmer <daniel@thingy.jp> + +description: | + MStar/SigmaStar's Armv7 SoCs that have more than one processor + have a region of registers that allow setting the boot address + and a magic number that allows secondary processors to leave + the loop they are parked in by the boot ROM. + +properties: + compatible: + items: + - enum: + - sstar,ssd201-smpctrl # SSD201/SSD202D + - const: mstar,smpctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + smpctrl@204000 { + compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl"; + reg = <0x204000 0x200>; + };
This adds a YAML description of the smpctrl node needed by the platform code for the MStar/SigmaStar Armv7 SoCs to boot secondary cpus. Signed-off-by: Daniel Palmer <daniel@0x0f.com> --- .../bindings/arm/mstar/mstar,smpctrl.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml