| Message ID | 20210111163711.12913-2-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Async flips for all ilk+ platforms | expand |
On 1/11/2021 10:07 PM, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Inform us if we're buggy and are about to exceed the size of the > bitfields in the plane TILEOFF/OFFSET registers. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Looks good to me. Reviewed-by: Karthik B S <karthik.b.s@intel.com> > --- > drivers/gpu/drm/i915/display/i9xx_plane.c | 7 +++++++ > drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ > 2 files changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c > index b78985c855a5..b1158ce4df92 100644 > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c > @@ -276,6 +276,13 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) > } > } > > + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { > + drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095); > + } else if (INTEL_GEN(dev_priv) >= 4 && > + fb->modifier == I915_FORMAT_MOD_X_TILED) { > + drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095); > + } > + > plane_state->color_plane[0].offset = offset; > plane_state->color_plane[0].x = src_x; > plane_state->color_plane[0].y = src_y; > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 0189d379a55e..7735c28b2467 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -3854,6 +3854,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) > } > } > > + drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191); > + > plane_state->color_plane[0].offset = offset; > plane_state->color_plane[0].x = x; > plane_state->color_plane[0].y = y; > @@ -3926,6 +3928,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) > } > } > > + drm_WARN_ON(&i915->drm, x > 8191 || y > 8191); > + > plane_state->color_plane[uv_plane].offset = offset; > plane_state->color_plane[uv_plane].x = x; > plane_state->color_plane[uv_plane].y = y;
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index b78985c855a5..b1158ce4df92 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -276,6 +276,13 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) } } + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { + drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095); + } else if (INTEL_GEN(dev_priv) >= 4 && + fb->modifier == I915_FORMAT_MOD_X_TILED) { + drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095); + } + plane_state->color_plane[0].offset = offset; plane_state->color_plane[0].x = src_x; plane_state->color_plane[0].y = src_y; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0189d379a55e..7735c28b2467 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3854,6 +3854,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) } } + drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191); + plane_state->color_plane[0].offset = offset; plane_state->color_plane[0].x = x; plane_state->color_plane[0].y = y; @@ -3926,6 +3928,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) } } + drm_WARN_ON(&i915->drm, x > 8191 || y > 8191); + plane_state->color_plane[uv_plane].offset = offset; plane_state->color_plane[uv_plane].x = x; plane_state->color_plane[uv_plane].y = y;