| Message ID | 20210203125913.390949-8-damien.lemoal@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RISC-V Kendryte K210 support improvements | expand |
On Wed, Feb 3, 2021 at 5:00 AM Damien Le Moal <damien.lemoal@wdc.com> wrote: > > The sifive gpio IP block supports up to 32 GPIOs. Reflect that in the > interrupts property description and maxItems. Also add the standard > ngpios property to describe the number of GPIOs available on the > implementation. > > Also add the "canaan,k210-gpiohs" compatible string to indicate the use > of this gpio controller in the Canaan Kendryte K210 SoC. If this > compatible string is used, do not define the clocks property as > required as the K210 SoC does not have a software controllable clock > for the Sifive gpio IP block. > > Cc: Paul Walmsley <paul.walmsley@sifive.com> > Cc: Rob Herring <robh@kernel.org> > Cc: devicetree@vger.kernel.org > Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> > --- > .../devicetree/bindings/gpio/sifive,gpio.yaml | 21 ++++++++++++++++--- > 1 file changed, 18 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml > index ab22056f8b44..2cef18ca737c 100644 > --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml > +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml > @@ -16,6 +16,7 @@ properties: > - enum: > - sifive,fu540-c000-gpio > - sifive,fu740-c000-gpio > + - canaan,k210-gpiohs > - const: sifive,gpio0 > > reg: > @@ -23,9 +24,9 @@ properties: > > interrupts: > description: > - interrupt mapping one per GPIO. Maximum 16 GPIOs. > + interrupt mapping one per GPIO. Maximum 32 GPIOs. > minItems: 1 > - maxItems: 16 > + maxItems: 32 > > interrupt-controller: true > > @@ -38,6 +39,10 @@ properties: > "#gpio-cells": > const: 2 > > + ngpios: > + minimum: 1 > + maximum: 32 > + > gpio-controller: true > > required: > @@ -46,10 +51,20 @@ required: > - interrupts > - interrupt-controller > - "#interrupt-cells" > - - clocks > - "#gpio-cells" > - gpio-controller > > +if: > + properties: > + compatible: > + contains: > + enum: > + - sifive,fu540-c000-gpio > + - sifive,fu740-c000-gpio > +then: > + required: > + - clocks > + > additionalProperties: false > > examples: > -- > 2.29.2 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Reviewed-by: Atish Patra <atish.patra@wdc.com>
diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml index ab22056f8b44..2cef18ca737c 100644 --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml @@ -16,6 +16,7 @@ properties: - enum: - sifive,fu540-c000-gpio - sifive,fu740-c000-gpio + - canaan,k210-gpiohs - const: sifive,gpio0 reg: @@ -23,9 +24,9 @@ properties: interrupts: description: - interrupt mapping one per GPIO. Maximum 16 GPIOs. + interrupt mapping one per GPIO. Maximum 32 GPIOs. minItems: 1 - maxItems: 16 + maxItems: 32 interrupt-controller: true @@ -38,6 +39,10 @@ properties: "#gpio-cells": const: 2 + ngpios: + minimum: 1 + maximum: 32 + gpio-controller: true required: @@ -46,10 +51,20 @@ required: - interrupts - interrupt-controller - "#interrupt-cells" - - clocks - "#gpio-cells" - gpio-controller +if: + properties: + compatible: + contains: + enum: + - sifive,fu540-c000-gpio + - sifive,fu740-c000-gpio +then: + required: + - clocks + additionalProperties: false examples:
The sifive gpio IP block supports up to 32 GPIOs. Reflect that in the interrupts property description and maxItems. Also add the standard ngpios property to describe the number of GPIOs available on the implementation. Also add the "canaan,k210-gpiohs" compatible string to indicate the use of this gpio controller in the Canaan Kendryte K210 SoC. If this compatible string is used, do not define the clocks property as required as the K210 SoC does not have a software controllable clock for the Sifive gpio IP block. Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> --- .../devicetree/bindings/gpio/sifive,gpio.yaml | 21 ++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-)