| Message ID | 75bbbe07-60c0-c556-41fa-8a4ddd117f5a@omprussia.ru (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 165bc5a4f30eee4735845aa7dbd6b738643f2603 |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | Fix TRSCER masks in the Ether driver | expand |
On Sun, Feb 28, 2021 at 9:56 PM Sergey Shtylyov <s.shtylyov@omprussia.ru> wrote: > According to the RZ/A2M Group User's Manual: Hardware, Rev. 2.00, > the TRSCER register has bit 9 reserved, hence we can't use the driver's > default TRSCER mask. Add the explicit initializer for sh_eth_cpu_data:: > trscer_err_mask for R7S9210. > > Fixes: 6e0bb04d0e4f ("sh_eth: Add R7S9210 support") > Signed-off-by: Sergey Shtylyov <s.shtylyov@omprussia.ru> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
Index: net/drivers/net/ethernet/renesas/sh_eth.c =================================================================== --- net.orig/drivers/net/ethernet/renesas/sh_eth.c +++ net/drivers/net/ethernet/renesas/sh_eth.c @@ -782,6 +782,8 @@ static struct sh_eth_cpu_data r7s9210_da .fdr_value = 0x0000070f, + .trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5, + .apr = 1, .mpr = 1, .tpauser = 1,
According to the RZ/A2M Group User's Manual: Hardware, Rev. 2.00, the TRSCER register has bit 9 reserved, hence we can't use the driver's default TRSCER mask. Add the explicit initializer for sh_eth_cpu_data:: trscer_err_mask for R7S9210. Fixes: 6e0bb04d0e4f ("sh_eth: Add R7S9210 support") Signed-off-by: Sergey Shtylyov <s.shtylyov@omprussia.ru> --- drivers/net/ethernet/renesas/sh_eth.c | 2 ++ 1 file changed, 2 insertions(+)