| Message ID | 20210305143259.12622-2-wsa+renesas@sang-engineering.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | v3u: add support for TMU | expand |
On Fri, Mar 5, 2021 at 3:33 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > Also add CL16MCK source clock for TMU0. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.13. Gr{oetje,eeting}s, Geert
Hi Wolfram, Thanks for your work. On 2021-03-05 15:32:57 +0100, Wolfram Sang wrote: > Also add CL16MCK source clock for TMU0. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > --- > drivers/clk/renesas/r8a779a0-cpg-mssr.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c > index 228068823caf..53bc2db0f3fc 100644 > --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c > @@ -144,6 +144,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { > DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1), > DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1), > DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1), > + DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1), > > DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870), > > @@ -192,6 +193,11 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { > DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0), > DEF_MOD("sydm1", 709, R8A779A0_CLK_S1D2), > DEF_MOD("sydm2", 710, R8A779A0_CLK_S1D2), > + DEF_MOD("tmu0", 713, R8A779A0_CLK_CL16MCK), > + DEF_MOD("tmu1", 714, R8A779A0_CLK_S1D4), > + DEF_MOD("tmu2", 715, R8A779A0_CLK_S1D4), > + DEF_MOD("tmu3", 716, R8A779A0_CLK_S1D4), > + DEF_MOD("tmu4", 717, R8A779A0_CLK_S1D4), > DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1), > DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1), > DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1), > -- > 2.29.2 >
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index 228068823caf..53bc2db0f3fc 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -144,6 +144,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1), DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1), DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1), + DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1), DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870), @@ -192,6 +193,11 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0), DEF_MOD("sydm1", 709, R8A779A0_CLK_S1D2), DEF_MOD("sydm2", 710, R8A779A0_CLK_S1D2), + DEF_MOD("tmu0", 713, R8A779A0_CLK_CL16MCK), + DEF_MOD("tmu1", 714, R8A779A0_CLK_S1D4), + DEF_MOD("tmu2", 715, R8A779A0_CLK_S1D4), + DEF_MOD("tmu3", 716, R8A779A0_CLK_S1D4), + DEF_MOD("tmu4", 717, R8A779A0_CLK_S1D4), DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1), DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1), DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1),
Also add CL16MCK source clock for TMU0. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- drivers/clk/renesas/r8a779a0-cpg-mssr.c | 6 ++++++ 1 file changed, 6 insertions(+)