| Message ID | 20210316015328.13516-1-liu@jiuyang.me (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Insert SFENCE.VMA in function set_pte_at for RISCV | expand |
Hi Jiuyang On Tue, Mar 16, 2021 at 1:56 AM Jiuyang Liu <liu@jiuyang.me> wrote: > > Sorry for the noise, Andrew gave me feedbacks, and pointed two bugs in > last patch. > 1. asid should be thread safe, which is not the intent. > 2. asid extracting logic was wrong. > > This patch fixes these bugs. > > Signed-off-by: Jiuyang Liu <liu@jiuyang.me> > --- > arch/riscv/include/asm/tlbflush.h | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h > index 4b25f51f163d..1f9b62b3670b 100644 > --- a/arch/riscv/include/asm/tlbflush.h > +++ b/arch/riscv/include/asm/tlbflush.h > @@ -22,10 +22,14 @@ static inline void local_flush_tlb_page(unsigned long addr) > __asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"); > } > > -static unsigned long asid; > +static inline unsigned long get_current_asid(void) > +{ > + return (csr_read(CSR_SATP) >> SATP_ASID_SHIFT) & SATP_ASID_MASK; > +} > + > static inline void local_flush_tlb_asid(void) > { > - asid = csr_read(CSR_SATP) | (SATP_ASID_MASK << SATP_ASID_SHIFT); > + unsigned long asid = get_current_asid(); > __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (asid) : "memory"); > } > This patch title is too obscure to parse, it should clearly reflect what's the changes doing here my two suggestions 1) if previous patches have already been merged, then you probably should fix title (the commit message) and re-send the patch? and maybe add a "Fixes" tag here 2) if previous patches still under reviewing.. then a) you can send an update patches series (can squash this fix) b) or maintainer willing to squash this fix for you?
On Tue, 16 Mar 2021 03:15:05 +0000 Yixun Lan <yixun.lan@gmail.com> wrote: > This patch title is too obscure to parse, it should clearly reflect > what's the changes doing here Yes please ;) Otherwise Andrew has to madly grep around to try to figure out what was Jiuyang Liu's "last patch"!
diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index 4b25f51f163d..1f9b62b3670b 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -22,10 +22,14 @@ static inline void local_flush_tlb_page(unsigned long addr) __asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"); } -static unsigned long asid; +static inline unsigned long get_current_asid(void) +{ + return (csr_read(CSR_SATP) >> SATP_ASID_SHIFT) & SATP_ASID_MASK; +} + static inline void local_flush_tlb_asid(void) { - asid = csr_read(CSR_SATP) | (SATP_ASID_MASK << SATP_ASID_SHIFT); + unsigned long asid = get_current_asid(); __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (asid) : "memory"); }
Sorry for the noise, Andrew gave me feedbacks, and pointed two bugs in last patch. 1. asid should be thread safe, which is not the intent. 2. asid extracting logic was wrong. This patch fixes these bugs. Signed-off-by: Jiuyang Liu <liu@jiuyang.me> --- arch/riscv/include/asm/tlbflush.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)