| Message ID | 20210304124316.164742-1-joel@jms.id.au (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | aspeed: Emulate the AST2600A3 | expand |
On 3/4/21 1:43 PM, Joel Stanley wrote: > This is the latest revision of the ASPEED 2600 SoC. > > Reset values are taken from v8 of the datasheet. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > include/hw/misc/aspeed_scu.h | 2 ++ > hw/arm/aspeed_ast2600.c | 2 +- > hw/misc/aspeed_scu.c | 32 +++++++++++++++++++++++++------- > 3 files changed, 28 insertions(+), 8 deletions(-) > -#define AST2600_CLK_SEL3 TO_REG(0x310) > +#define AST2600_CLK_SEL3 TO_REG(0x308) This register doesn't seem in use, still it would be nice to mention this fix in the commit description.
On 3/4/21 1:43 PM, Joel Stanley wrote: > This is the latest revision of the ASPEED 2600 SoC. Should we change all machines to use the new SoC ? I would prefer if we introduced an "ast2600-a3" Aspeed SoC, that we would use for the newer rainier machine, and leave the tacoma-bmc and ast2600-evb machines as they are. Thanks, C. > Reset values are taken from v8 of the datasheet. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > include/hw/misc/aspeed_scu.h | 2 ++ > hw/arm/aspeed_ast2600.c | 2 +- > hw/misc/aspeed_scu.c | 32 +++++++++++++++++++++++++------- > 3 files changed, 28 insertions(+), 8 deletions(-) > > diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h > index d49bfb02fbdb..c14aff2bcbb5 100644 > --- a/include/hw/misc/aspeed_scu.h > +++ b/include/hw/misc/aspeed_scu.h > @@ -43,6 +43,8 @@ struct AspeedSCUState { > #define AST2500_A1_SILICON_REV 0x04010303U > #define AST2600_A0_SILICON_REV 0x05000303U > #define AST2600_A1_SILICON_REV 0x05010303U > +#define AST2600_A2_SILICON_REV 0x05020303U > +#define AST2600_A3_SILICON_REV 0x05030303U > > #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) > > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c > index bf31ca351feb..8c42dafe8583 100644 > --- a/hw/arm/aspeed_ast2600.c > +++ b/hw/arm/aspeed_ast2600.c > @@ -480,7 +480,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) > > sc->name = "ast2600-a1"; > sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); > - sc->silicon_rev = AST2600_A1_SILICON_REV; > + sc->silicon_rev = AST2600_A3_SILICON_REV; > sc->sram_size = 0x16400; > sc->spis_num = 2; > sc->ehcis_num = 2; > diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c > index 40a38ebd8549..3515d6ff6bbf 100644 > --- a/hw/misc/aspeed_scu.c > +++ b/hw/misc/aspeed_scu.c > @@ -104,11 +104,19 @@ > #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100) > #define AST2600_HPLL_PARAM TO_REG(0x200) > #define AST2600_HPLL_EXT TO_REG(0x204) > +#define AST2600_APLL_PARAM TO_REG(0x210) > +#define AST2600_APLL_EXT TO_REG(0x214) > +#define AST2600_MPLL_PARAM TO_REG(0x220) > #define AST2600_MPLL_EXT TO_REG(0x224) > +#define AST2600_EPLL_PARAM TO_REG(0x240) > #define AST2600_EPLL_EXT TO_REG(0x244) > +#define AST2600_DPLL_PARAM TO_REG(0x260) > +#define AST2600_DPLL_EXT TO_REG(0x264) > #define AST2600_CLK_SEL TO_REG(0x300) > #define AST2600_CLK_SEL2 TO_REG(0x304) > -#define AST2600_CLK_SEL3 TO_REG(0x310) > +#define AST2600_CLK_SEL3 TO_REG(0x308) > +#define AST2600_CLK_SEL4 TO_REG(0x310) > +#define AST2600_CLK_SEL5 TO_REG(0x314) > #define AST2600_HW_STRAP1 TO_REG(0x500) > #define AST2600_HW_STRAP1_CLR TO_REG(0x504) > #define AST2600_HW_STRAP1_PROT TO_REG(0x508) > @@ -433,6 +441,8 @@ static uint32_t aspeed_silicon_revs[] = { > AST2500_A1_SILICON_REV, > AST2600_A0_SILICON_REV, > AST2600_A1_SILICON_REV, > + AST2600_A2_SILICON_REV, > + AST2600_A3_SILICON_REV, > }; > > bool is_supported_silicon_rev(uint32_t silicon_rev) > @@ -651,16 +661,24 @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = { > .valid.unaligned = false, > }; > > -static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = { > +static const uint32_t ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = { > [AST2600_SYS_RST_CTRL] = 0xF7C3FED8, > - [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC, > + [AST2600_SYS_RST_CTRL2] = 0x0DFFFFFC, > [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A, > [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, > [AST2600_SDRAM_HANDSHAKE] = 0x00000000, > - [AST2600_HPLL_PARAM] = 0x1000405F, > + [AST2600_HPLL_PARAM] = 0x1000408F, > + [AST2600_APLL_PARAM] = 0x1000405F, > + [AST2600_MPLL_PARAM] = 0x1008405F, > + [AST2600_EPLL_PARAM] = 0x1004077F, > + [AST2600_DPLL_PARAM] = 0x1078405F, > + [AST2600_CLK_SEL] = 0xF3940000, > + [AST2600_CLK_SEL2] = 0x00700000, > + [AST2600_CLK_SEL3] = 0x00000000, > + [AST2600_CLK_SEL4] = 0xF3F40000, > + [AST2600_CLK_SEL5] = 0x30000000, > [AST2600_CHIP_ID0] = 0x1234ABCD, > [AST2600_CHIP_ID1] = 0x88884444, > - > }; > > static void aspeed_ast2600_scu_reset(DeviceState *dev) > @@ -675,7 +693,7 @@ static void aspeed_ast2600_scu_reset(DeviceState *dev) > * of actual revision. QEMU and Linux only support A1 onwards so this is > * sufficient. > */ > - s->regs[AST2600_SILICON_REV] = AST2600_A1_SILICON_REV; > + s->regs[AST2600_SILICON_REV] = AST2600_A3_SILICON_REV; > s->regs[AST2600_SILICON_REV2] = s->silicon_rev; > s->regs[AST2600_HW_STRAP1] = s->hw_strap1; > s->regs[AST2600_HW_STRAP2] = s->hw_strap2; > @@ -689,7 +707,7 @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data) > > dc->desc = "ASPEED 2600 System Control Unit"; > dc->reset = aspeed_ast2600_scu_reset; > - asc->resets = ast2600_a1_resets; > + asc->resets = ast2600_a3_resets; > asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */ > asc->apb_divider = 4; > asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS; >
On Tue, 13 Apr 2021, at 00:57, Cédric Le Goater wrote: > On 3/4/21 1:43 PM, Joel Stanley wrote: > > This is the latest revision of the ASPEED 2600 SoC. > > Should we change all machines to use the new SoC ? > > I would prefer if we introduced an "ast2600-a3" Aspeed SoC, that we would > use for the newer rainier machine, and leave the tacoma-bmc and ast2600-evb > machines as they are. I think we just change them all. We're not going to see pre-A3 chips in production systems. Andrew
On Mon, 12 Apr 2021 at 22:57, Andrew Jeffery <andrew@aj.id.au> wrote: > > > > On Tue, 13 Apr 2021, at 00:57, Cédric Le Goater wrote: > > On 3/4/21 1:43 PM, Joel Stanley wrote: > > > This is the latest revision of the ASPEED 2600 SoC. > > > > Should we change all machines to use the new SoC ? > > > > I would prefer if we introduced an "ast2600-a3" Aspeed SoC, that we would > > use for the newer rainier machine, and leave the tacoma-bmc and ast2600-evb > > machines as they are. > > I think we just change them all. We're not going to see pre-A3 chips in > production systems. We should split this patch into two. The A3 support is not yet present in any u-boot tree, so it would be premature to update any socs to emulate the A3. We can expect support in the coming months, and when that lands we can consider updating. However filling out some of the clock register reset values is important for guests to calculate sensible clock rates, so we should do that now for the A1. Cheers, Joel
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index d49bfb02fbdb..c14aff2bcbb5 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -43,6 +43,8 @@ struct AspeedSCUState { #define AST2500_A1_SILICON_REV 0x04010303U #define AST2600_A0_SILICON_REV 0x05000303U #define AST2600_A1_SILICON_REV 0x05010303U +#define AST2600_A2_SILICON_REV 0x05020303U +#define AST2600_A3_SILICON_REV 0x05030303U #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index bf31ca351feb..8c42dafe8583 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -480,7 +480,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) sc->name = "ast2600-a1"; sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); - sc->silicon_rev = AST2600_A1_SILICON_REV; + sc->silicon_rev = AST2600_A3_SILICON_REV; sc->sram_size = 0x16400; sc->spis_num = 2; sc->ehcis_num = 2; diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 40a38ebd8549..3515d6ff6bbf 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -104,11 +104,19 @@ #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100) #define AST2600_HPLL_PARAM TO_REG(0x200) #define AST2600_HPLL_EXT TO_REG(0x204) +#define AST2600_APLL_PARAM TO_REG(0x210) +#define AST2600_APLL_EXT TO_REG(0x214) +#define AST2600_MPLL_PARAM TO_REG(0x220) #define AST2600_MPLL_EXT TO_REG(0x224) +#define AST2600_EPLL_PARAM TO_REG(0x240) #define AST2600_EPLL_EXT TO_REG(0x244) +#define AST2600_DPLL_PARAM TO_REG(0x260) +#define AST2600_DPLL_EXT TO_REG(0x264) #define AST2600_CLK_SEL TO_REG(0x300) #define AST2600_CLK_SEL2 TO_REG(0x304) -#define AST2600_CLK_SEL3 TO_REG(0x310) +#define AST2600_CLK_SEL3 TO_REG(0x308) +#define AST2600_CLK_SEL4 TO_REG(0x310) +#define AST2600_CLK_SEL5 TO_REG(0x314) #define AST2600_HW_STRAP1 TO_REG(0x500) #define AST2600_HW_STRAP1_CLR TO_REG(0x504) #define AST2600_HW_STRAP1_PROT TO_REG(0x508) @@ -433,6 +441,8 @@ static uint32_t aspeed_silicon_revs[] = { AST2500_A1_SILICON_REV, AST2600_A0_SILICON_REV, AST2600_A1_SILICON_REV, + AST2600_A2_SILICON_REV, + AST2600_A3_SILICON_REV, }; bool is_supported_silicon_rev(uint32_t silicon_rev) @@ -651,16 +661,24 @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = { .valid.unaligned = false, }; -static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = { +static const uint32_t ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = { [AST2600_SYS_RST_CTRL] = 0xF7C3FED8, - [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC, + [AST2600_SYS_RST_CTRL2] = 0x0DFFFFFC, [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A, [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, [AST2600_SDRAM_HANDSHAKE] = 0x00000000, - [AST2600_HPLL_PARAM] = 0x1000405F, + [AST2600_HPLL_PARAM] = 0x1000408F, + [AST2600_APLL_PARAM] = 0x1000405F, + [AST2600_MPLL_PARAM] = 0x1008405F, + [AST2600_EPLL_PARAM] = 0x1004077F, + [AST2600_DPLL_PARAM] = 0x1078405F, + [AST2600_CLK_SEL] = 0xF3940000, + [AST2600_CLK_SEL2] = 0x00700000, + [AST2600_CLK_SEL3] = 0x00000000, + [AST2600_CLK_SEL4] = 0xF3F40000, + [AST2600_CLK_SEL5] = 0x30000000, [AST2600_CHIP_ID0] = 0x1234ABCD, [AST2600_CHIP_ID1] = 0x88884444, - }; static void aspeed_ast2600_scu_reset(DeviceState *dev) @@ -675,7 +693,7 @@ static void aspeed_ast2600_scu_reset(DeviceState *dev) * of actual revision. QEMU and Linux only support A1 onwards so this is * sufficient. */ - s->regs[AST2600_SILICON_REV] = AST2600_A1_SILICON_REV; + s->regs[AST2600_SILICON_REV] = AST2600_A3_SILICON_REV; s->regs[AST2600_SILICON_REV2] = s->silicon_rev; s->regs[AST2600_HW_STRAP1] = s->hw_strap1; s->regs[AST2600_HW_STRAP2] = s->hw_strap2; @@ -689,7 +707,7 @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data) dc->desc = "ASPEED 2600 System Control Unit"; dc->reset = aspeed_ast2600_scu_reset; - asc->resets = ast2600_a1_resets; + asc->resets = ast2600_a3_resets; asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */ asc->apb_divider = 4; asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
This is the latest revision of the ASPEED 2600 SoC. Reset values are taken from v8 of the datasheet. Signed-off-by: Joel Stanley <joel@jms.id.au> --- include/hw/misc/aspeed_scu.h | 2 ++ hw/arm/aspeed_ast2600.c | 2 +- hw/misc/aspeed_scu.c | 32 +++++++++++++++++++++++++------- 3 files changed, 28 insertions(+), 8 deletions(-)