@@ -164,7 +164,15 @@
#define CLK_TOP_APLL12_DIV9 152
#define CLK_TOP_SSUSB_TOP_REF 153
#define CLK_TOP_SSUSB_PHY_REF 154
-#define CLK_TOP_NR_CLK 155
+#define CLK_TOP_DSP_SEL 155
+#define CLK_TOP_DSP1_SEL 156
+#define CLK_TOP_DSP1_NPUPLL_SEL 157
+#define CLK_TOP_DSP2_SEL 158
+#define CLK_TOP_DSP2_NPUPLL_SEL 159
+#define CLK_TOP_DSP5_SEL 160
+#define CLK_TOP_DSP5_APUPLL_SEL 161
+#define CLK_TOP_IPU_IF_SEL 162
+#define CLK_TOP_NR_CLK 163
/* INFRACFG */
@@ -309,7 +317,9 @@
#define CLK_APMIXED_APLL1 8
#define CLK_APMIXED_APLL2 9
#define CLK_APMIXED_MIPID26M 10
-#define CLK_APMIXED_NR_CLK 11
+#define CLK_APMIXED_APUPLL 11
+#define CLK_APMIXED_NPUPLL 12
+#define CLK_APMIXED_NR_CLK 13
/* SCP_ADSP */