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[11/26] target/mips: Move cpu_signal_handler definition around

Message ID 20210418163134.1133100-12-f4bug@amsat.org (mailing list archive)
State New, archived
Headers show
Series target/mips: Re-org to allow KVM-only builds | expand

Commit Message

Philippe Mathieu-Daudé April 18, 2021, 4:31 p.m. UTC
We have 2 blocks guarded with #ifdef for sysemu, which
are simply separated by the cpu_signal_handler definition.

To simplify the following commits which involve various
changes in internal.h, first join the sysemu-guarded blocks.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/internal.h | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

Comments

Richard Henderson April 18, 2021, 7:13 p.m. UTC | #1
On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:
> We have 2 blocks guarded with #ifdef for sysemu, which
> are simply separated by the cpu_signal_handler definition.
> 
> To simplify the following commits which involve various
> changes in internal.h, first join the sysemu-guarded blocks.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/internal.h | 9 ++++-----
>   1 file changed, 4 insertions(+), 5 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/mips/internal.h b/target/mips/internal.h
index b3427fcc517..294560c9d2f 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -151,14 +151,13 @@  void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
                                     MemTxResult response, uintptr_t retaddr);
 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
                                   MMUAccessType access_type);
-#endif
+
+extern const VMStateDescription vmstate_mips_cpu;
+
+#endif /* !CONFIG_USER_ONLY */
 
 #define cpu_signal_handler cpu_mips_signal_handler
 
-#ifndef CONFIG_USER_ONLY
-extern const VMStateDescription vmstate_mips_cpu;
-#endif
-
 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
 {
     return (env->CP0_Status & (1 << CP0St_IE)) &&