| Message ID | 20210721224610.3035258-1-bjorn.andersson@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | clk: qcom: dispcc-sm8250: Add additional parent clocks for DP | expand |
On 22/07/2021 01:46, Bjorn Andersson wrote: > The clock controller has two additional clock source pairs, in order to > support more than a single DisplayPort PHY. List these, so it's possible > to describe them all. > > Also drop the unnecessary freq_tbl for the link clock sources, to allow > these parents to be used. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/clk/qcom/dispcc-sm8250.c | 22 ++++++++++++---------- > 1 file changed, 12 insertions(+), 10 deletions(-) > > diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c > index 601c7c0ba483..bf9ffe1a1cf4 100644 > --- a/drivers/clk/qcom/dispcc-sm8250.c > +++ b/drivers/clk/qcom/dispcc-sm8250.c > @@ -26,6 +26,10 @@ enum { > P_DISP_CC_PLL1_OUT_MAIN, > P_DP_PHY_PLL_LINK_CLK, > P_DP_PHY_PLL_VCO_DIV_CLK, > + P_DPTX1_PHY_PLL_LINK_CLK, > + P_DPTX1_PHY_PLL_VCO_DIV_CLK, > + P_DPTX2_PHY_PLL_LINK_CLK, > + P_DPTX2_PHY_PLL_VCO_DIV_CLK, > P_EDP_PHY_PLL_LINK_CLK, > P_EDP_PHY_PLL_VCO_DIV_CLK, > P_DSI0_PHY_PLL_OUT_BYTECLK, > @@ -98,12 +102,20 @@ static const struct parent_map disp_cc_parent_map_0[] = { > { P_BI_TCXO, 0 }, > { P_DP_PHY_PLL_LINK_CLK, 1 }, > { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, > + { P_DPTX1_PHY_PLL_LINK_CLK, 3 }, > + { P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 }, > + { P_DPTX2_PHY_PLL_LINK_CLK, 5 }, > + { P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 }, > }; > > static const struct clk_parent_data disp_cc_parent_data_0[] = { > { .fw_name = "bi_tcxo" }, > { .fw_name = "dp_phy_pll_link_clk" }, > { .fw_name = "dp_phy_pll_vco_div_clk" }, > + { .fw_name = "dptx1_phy_pll_link_clk" }, > + { .fw_name = "dptx1_phy_pll_vco_div_clk" }, > + { .fw_name = "dptx2_phy_pll_link_clk" }, > + { .fw_name = "dptx2_phy_pll_vco_div_clk" }, > }; > > static const struct parent_map disp_cc_parent_map_1[] = { > @@ -269,20 +281,11 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { > }, > }; > > -static const struct freq_tbl ftbl_disp_cc_mdss_dp_link1_clk_src[] = { > - F(162000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(270000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(540000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(810000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - { } > -}; > - > static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { > .cmd_rcgr = 0x220c, > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_0, > - .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src, > .clkr.hw.init = &(struct clk_init_data){ > .name = "disp_cc_mdss_dp_link1_clk_src", > .parent_data = disp_cc_parent_data_0, > @@ -296,7 +299,6 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_0, > - .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src, > .clkr.hw.init = &(struct clk_init_data){ > .name = "disp_cc_mdss_dp_link_clk_src", > .parent_data = disp_cc_parent_data_0, >
Quoting Bjorn Andersson (2021-07-21 15:46:10) > The clock controller has two additional clock source pairs, in order to > support more than a single DisplayPort PHY. List these, so it's possible > to describe them all. > > Also drop the unnecessary freq_tbl for the link clock sources, to allow > these parents to be used. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- Applied to clk-next
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 601c7c0ba483..bf9ffe1a1cf4 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -26,6 +26,10 @@ enum { P_DISP_CC_PLL1_OUT_MAIN, P_DP_PHY_PLL_LINK_CLK, P_DP_PHY_PLL_VCO_DIV_CLK, + P_DPTX1_PHY_PLL_LINK_CLK, + P_DPTX1_PHY_PLL_VCO_DIV_CLK, + P_DPTX2_PHY_PLL_LINK_CLK, + P_DPTX2_PHY_PLL_VCO_DIV_CLK, P_EDP_PHY_PLL_LINK_CLK, P_EDP_PHY_PLL_VCO_DIV_CLK, P_DSI0_PHY_PLL_OUT_BYTECLK, @@ -98,12 +102,20 @@ static const struct parent_map disp_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_DP_PHY_PLL_LINK_CLK, 1 }, { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, + { P_DPTX1_PHY_PLL_LINK_CLK, 3 }, + { P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 }, + { P_DPTX2_PHY_PLL_LINK_CLK, 5 }, + { P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 }, }; static const struct clk_parent_data disp_cc_parent_data_0[] = { { .fw_name = "bi_tcxo" }, { .fw_name = "dp_phy_pll_link_clk" }, { .fw_name = "dp_phy_pll_vco_div_clk" }, + { .fw_name = "dptx1_phy_pll_link_clk" }, + { .fw_name = "dptx1_phy_pll_vco_div_clk" }, + { .fw_name = "dptx2_phy_pll_link_clk" }, + { .fw_name = "dptx2_phy_pll_vco_div_clk" }, }; static const struct parent_map disp_cc_parent_map_1[] = { @@ -269,20 +281,11 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { }, }; -static const struct freq_tbl ftbl_disp_cc_mdss_dp_link1_clk_src[] = { - F(162000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(270000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(540000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(810000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - { } -}; - static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { .cmd_rcgr = 0x220c, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_0, - .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link1_clk_src", .parent_data = disp_cc_parent_data_0, @@ -296,7 +299,6 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_0, - .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_clk_src", .parent_data = disp_cc_parent_data_0,
The clock controller has two additional clock source pairs, in order to support more than a single DisplayPort PHY. List these, so it's possible to describe them all. Also drop the unnecessary freq_tbl for the link clock sources, to allow these parents to be used. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- drivers/clk/qcom/dispcc-sm8250.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-)