| Message ID | 20210807145537.124744-1-xianting.tian@linux.alibaba.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: add ARCH_DMA_MINALIGN support | expand |
On Sat, 7 Aug 2021 22:55:37 +0800 Xianting Tian <xianting.tian@linux.alibaba.com> wrote: > Introduce ARCH_DMA_MINALIGN to riscv arch. > > Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com> > --- > arch/riscv/include/asm/cache.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h > index 9b58b1045..2945bbe2b 100644 > --- a/arch/riscv/include/asm/cache.h > +++ b/arch/riscv/include/asm/cache.h > @@ -11,6 +11,8 @@ > > #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) > > +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES It's not a good idea to blindly set this for all riscv. For "coherent" platforms, this is not necessary and will waste memory. > + > /* > * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that > * the flat loader aligns it accordingly.
在 2021/8/9 上午12:30, Jisheng Zhang 写道: > On Sat, 7 Aug 2021 22:55:37 +0800 > Xianting Tian <xianting.tian@linux.alibaba.com> wrote: > >> Introduce ARCH_DMA_MINALIGN to riscv arch. >> >> Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com> >> --- >> arch/riscv/include/asm/cache.h | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h >> index 9b58b1045..2945bbe2b 100644 >> --- a/arch/riscv/include/asm/cache.h >> +++ b/arch/riscv/include/asm/cache.h >> @@ -11,6 +11,8 @@ >> >> #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) >> >> +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES > It's not a good idea to blindly set this for all riscv. For "coherent" > platforms, this is not necessary and will waste memory. > thanks for the reply, So riscv is the "coherent" platform? I submit this patch as I got a fix suggestion of another patch to use ARCH_DMA_MINALIGN, but riscv doesn't define it. https://lkml.org/lkml/2021/8/6/723 <https://lkml.org/lkml/2021/8/6/723> Considering the portability of the code, in my opinion, it is better to define it for riscv if it is not "coherent" platform. >> + >> /* >> * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that >> * the flat loader aligns it accordingly.
在 2021/8/9 上午12:30, Jisheng Zhang 写道: > On Sat, 7 Aug 2021 22:55:37 +0800 > Xianting Tian <xianting.tian@linux.alibaba.com> wrote: > >> Introduce ARCH_DMA_MINALIGN to riscv arch. >> >> Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com> >> --- >> arch/riscv/include/asm/cache.h | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h >> index 9b58b1045..2945bbe2b 100644 >> --- a/arch/riscv/include/asm/cache.h >> +++ b/arch/riscv/include/asm/cache.h >> @@ -11,6 +11,8 @@ >> >> #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) >> >> +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES > It's not a good idea to blindly set this for all riscv. For "coherent" > platforms, this is not necessary and will waste memory. I checked ARCH_DMA_MINALIGN definition, "If an architecture isn't fully DMA-coherent, ARCH_DMA_MINALIGN must be set". so that the memory allocator makes sure that kmalloc'ed buffer doesn't share a cache line with the others. Documentation/core-api/dma-api-howto.rst 2) ARCH_DMA_MINALIGN Architectures must ensure that kmalloc'ed buffer is DMA-safe. Drivers and subsystems depend on it. If an architecture isn't fully DMA-coherent (i.e. hardware doesn't ensure that data in the CPU cache is identical to data in main memory), ARCH_DMA_MINALIGN must be set so that the memory allocator makes sure that kmalloc'ed buffer doesn't share a cache line with the others. See arch/arm/include/asm/cache.h as an example. Note that ARCH_DMA_MINALIGN is about DMA memory alignment constraints. You don't need to worry about the architecture data alignment constraints (e.g. the alignment constraints about 64-bit objects). > >> + >> /* >> * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that >> * the flat loader aligns it accordingly.
On Mon, Aug 9, 2021 at 8:20 AM Xianting TIan <xianting.tian@linux.alibaba.com> wrote: > > >> +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES > > It's not a good idea to blindly set this for all riscv. For "coherent" > > platforms, this is not necessary and will waste memory. > > I checked ARCH_DMA_MINALIGN definition, "If an architecture isn't fully > DMA-coherent, ARCH_DMA_MINALIGN must be set". > > so that the memory allocator makes sure that kmalloc'ed buffer doesn't > share a cache line with the others. > > Documentation/core-api/dma-api-howto.rst > > 2) ARCH_DMA_MINALIGN > > Architectures must ensure that kmalloc'ed buffer is > DMA-safe. Drivers and subsystems depend on it. If an architecture > isn't fully DMA-coherent (i.e. hardware doesn't ensure that data in > the CPU cache is identical to data in main memory), > ARCH_DMA_MINALIGN must be set so that the memory allocator > makes sure that kmalloc'ed buffer doesn't share a cache line with > the others. See arch/arm/include/asm/cache.h as an example. > > Note that ARCH_DMA_MINALIGN is about DMA memory alignment > constraints. You don't need to worry about the architecture data > alignment constraints (e.g. the alignment constraints about 64-bit > objects). The platform spec [1] says about this: | Memory accesses by I/O masters can be coherent or non-coherent | with respect to all hart-related caches. So the kernel in its default configuration can not assume that DMA is cache coherent on RISC-V. Making this configurable implies that a kernel that is configured for cache-coherent machines can no longer run on all hardware that follows the platform spec. We have the same problem on arm64, where most of the server parts are cache coherent, but the majority of the low-end embedded devices are not, and we require that a single kernel ran run on all of the above. One idea that we have discussed several times is to start the kernel without the small kmalloc caches and defer their creation until a later point in the boot process after determining whether any non-coherent devices have been discovered. Any in-kernel structures that have an explicit ARCH_DMA_MINALIGN alignment won't benefit from this, but any subsequent kmalloc() calls can use the smaller caches. The tricky bit is finding out whether /everything/ on the system is cache-coherent or not, since we do not have a global flag for that in the DT. See [2] for a recent discussion. Arnd [1] https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.adoc#architecture [2] https://lore.kernel.org/linux-arm-kernel/20210527124356.22367-1-will@kernel.org/
在 2021/8/9 下午3:49, Arnd Bergmann 写道: > On Mon, Aug 9, 2021 at 8:20 AM Xianting TIan > <xianting.tian@linux.alibaba.com> wrote: >>>> +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES >>> It's not a good idea to blindly set this for all riscv. For "coherent" >>> platforms, this is not necessary and will waste memory. >> I checked ARCH_DMA_MINALIGN definition, "If an architecture isn't fully >> DMA-coherent, ARCH_DMA_MINALIGN must be set". >> >> so that the memory allocator makes sure that kmalloc'ed buffer doesn't >> share a cache line with the others. >> >> Documentation/core-api/dma-api-howto.rst >> >> 2) ARCH_DMA_MINALIGN >> >> Architectures must ensure that kmalloc'ed buffer is >> DMA-safe. Drivers and subsystems depend on it. If an architecture >> isn't fully DMA-coherent (i.e. hardware doesn't ensure that data in >> the CPU cache is identical to data in main memory), >> ARCH_DMA_MINALIGN must be set so that the memory allocator >> makes sure that kmalloc'ed buffer doesn't share a cache line with >> the others. See arch/arm/include/asm/cache.h as an example. >> >> Note that ARCH_DMA_MINALIGN is about DMA memory alignment >> constraints. You don't need to worry about the architecture data >> alignment constraints (e.g. the alignment constraints about 64-bit >> objects). > The platform spec [1] says about this: > > | Memory accesses by I/O masters can be coherent or non-coherent > | with respect to all hart-related caches. > > So the kernel in its default configuration can not assume that DMA is > cache coherent on RISC-V. Making this configurable implies that > a kernel that is configured for cache-coherent machines can no longer > run on all hardware that follows the platform spec. > > We have the same problem on arm64, where most of the server parts > are cache coherent, but the majority of the low-end embedded devices > are not, and we require that a single kernel ran run on all of the above. > > One idea that we have discussed several times is to start the kernel > without the small kmalloc caches and defer their creation until a > later point in the boot process after determining whether any > non-coherent devices have been discovered. Any in-kernel structures > that have an explicit ARCH_DMA_MINALIGN alignment won't > benefit from this, but any subsequent kmalloc() calls can use the > smaller caches. The tricky bit is finding out whether /everything/ on > the system is cache-coherent or not, since we do not have a global > flag for that in the DT. See [2] for a recent discussion. > > Arnd > > [1] https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.adoc#architecture > [2] https://lore.kernel.org/linux-arm-kernel/20210527124356.22367-1-will@kernel.org/ Arnd, thanks for info, according to the description, seems we need to apply this patch to riscv.
On Mon, Aug 9, 2021 at 12:50 AM Arnd Bergmann <arnd@kernel.org> wrote: > > On Mon, Aug 9, 2021 at 8:20 AM Xianting TIan > <xianting.tian@linux.alibaba.com> wrote: > > > > >> +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES > > > It's not a good idea to blindly set this for all riscv. For "coherent" > > > platforms, this is not necessary and will waste memory. > > > > I checked ARCH_DMA_MINALIGN definition, "If an architecture isn't fully > > DMA-coherent, ARCH_DMA_MINALIGN must be set". > > > > so that the memory allocator makes sure that kmalloc'ed buffer doesn't > > share a cache line with the others. > > > > Documentation/core-api/dma-api-howto.rst > > > > 2) ARCH_DMA_MINALIGN > > > > Architectures must ensure that kmalloc'ed buffer is > > DMA-safe. Drivers and subsystems depend on it. If an architecture > > isn't fully DMA-coherent (i.e. hardware doesn't ensure that data in > > the CPU cache is identical to data in main memory), > > ARCH_DMA_MINALIGN must be set so that the memory allocator > > makes sure that kmalloc'ed buffer doesn't share a cache line with > > the others. See arch/arm/include/asm/cache.h as an example. > > > > Note that ARCH_DMA_MINALIGN is about DMA memory alignment > > constraints. You don't need to worry about the architecture data > > alignment constraints (e.g. the alignment constraints about 64-bit > > objects). > > The platform spec [1] says about this: > > | Memory accesses by I/O masters can be coherent or non-coherent > | with respect to all hart-related caches. > > So the kernel in its default configuration can not assume that DMA is > cache coherent on RISC-V. Making this configurable implies that > a kernel that is configured for cache-coherent machines can no longer > run on all hardware that follows the platform spec. > > We have the same problem on arm64, where most of the server parts > are cache coherent, but the majority of the low-end embedded devices > are not, and we require that a single kernel ran run on all of the above. > > One idea that we have discussed several times is to start the kernel > without the small kmalloc caches and defer their creation until a > later point in the boot process after determining whether any > non-coherent devices have been discovered. Any in-kernel structures > that have an explicit ARCH_DMA_MINALIGN alignment won't > benefit from this, but any subsequent kmalloc() calls can use the > smaller caches. The tricky bit is finding out whether /everything/ on > the system is cache-coherent or not, since we do not have a global > flag for that in the DT. See [2] for a recent discussion. Can we add a new DT property to indicate the system is fully cache-coherent ? That will be helpful for RISC-V as well. We already have platforms like hifive unleashed/unmatched that are coherent while beagleV is not. The workaround to support both platforms in a single image was not very pretty [1]. [1] https://patchwork.kernel.org/project/linux-riscv/list/?series=520541 > > Arnd > > [1] https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.adoc#architecture > [2] https://lore.kernel.org/linux-arm-kernel/20210527124356.22367-1-will@kernel.org/ > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Mon, Aug 9, 2021 at 9:55 AM Xianting TIan <xianting.tian@linux.alibaba.com> wrote: > > > 在 2021/8/9 上午12:30, Jisheng Zhang 写道: > > On Sat, 7 Aug 2021 22:55:37 +0800 > > Xianting Tian <xianting.tian@linux.alibaba.com> wrote: > > > >> Introduce ARCH_DMA_MINALIGN to riscv arch. > >> > >> Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com> > >> --- > >> arch/riscv/include/asm/cache.h | 2 ++ > >> 1 file changed, 2 insertions(+) > >> > >> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h > >> index 9b58b1045..2945bbe2b 100644 > >> --- a/arch/riscv/include/asm/cache.h > >> +++ b/arch/riscv/include/asm/cache.h > >> @@ -11,6 +11,8 @@ > >> > >> #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) > >> > >> +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES > > It's not a good idea to blindly set this for all riscv. For "coherent" > > platforms, this is not necessary and will waste memory. quote from slab.h: * Some archs want to perform DMA into kmalloc caches and need a guaranteed * alignment larger than the alignment of a 64-bit integer. * Setting ARCH_KMALLOC_MINALIGN in arch headers allows that. ARCH_DMA_MINALIGN is for the whole system, maybe we could give a DMA_MINALIGN Kconfig entry in arch/riscv? > > > thanks for the reply, > > So riscv is the "coherent" platform? > > I submit this patch as I got a fix suggestion of another patch to use > ARCH_DMA_MINALIGN, but riscv doesn't define it. > > https://lkml.org/lkml/2021/8/6/723 <https://lkml.org/lkml/2021/8/6/723> > > Considering the portability of the code, in my opinion, it is better to > define it for riscv if it is not "coherent" platform. > > >> + > >> /* > >> * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that > >> * the flat loader aligns it accordingly.
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index 9b58b1045..2945bbe2b 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -11,6 +11,8 @@ #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES + /* * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that * the flat loader aligns it accordingly.
Introduce ARCH_DMA_MINALIGN to riscv arch. Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com> --- arch/riscv/include/asm/cache.h | 2 ++ 1 file changed, 2 insertions(+)