| Message ID | 20210809131556.686260-9-clg@kaod.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Aspeed: 6.2 queue | expand |
On 8/9/21 3:15 PM, Cédric Le Goater wrote: > From: Joel Stanley <joel@jms.id.au> > > This is the latest revision of the ASPEED 2600 SoC. As there is no > need to model multiple revisions of the same SoC for the moment, > update the SCU AST2600 to model the A3 revision instead of the A1 and > adapt the AST2600 SoC and machines. > > Reset values are taken from v8 of the datasheet. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > [ clg: - Introduced an Aspeed "ast2600-a3" SoC class > - Commit log update ] > Message-Id: <20210407171637.777743-21-clg@kaod.org> > Signed-off-by: Cédric Le Goater <clg@kaod.org> > Message-Id: <20210629142336.750058-3-clg@kaod.org> > Signed-off-by: Cédric Le Goater <clg@kaod.org> > --- > include/hw/misc/aspeed_scu.h | 2 ++ > hw/arm/aspeed.c | 6 +++--- > hw/arm/aspeed_ast2600.c | 6 +++--- > hw/misc/aspeed_scu.c | 36 +++++++++++++++++++++++++++++------- > 4 files changed, 37 insertions(+), 13 deletions(-) > diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c > index 40a38ebd8549..05edebedeb46 100644 > --- a/hw/misc/aspeed_scu.c > +++ b/hw/misc/aspeed_scu.c > @@ -101,14 +101,24 @@ > #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) > #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) > #define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94) > +#define AST2600_DEBUG_CTRL TO_REG(0xC8) > +#define AST2600_DEBUG_CTRL2 TO_REG(0xD8) > #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100) > #define AST2600_HPLL_PARAM TO_REG(0x200) > #define AST2600_HPLL_EXT TO_REG(0x204) > +#define AST2600_APLL_PARAM TO_REG(0x210) > +#define AST2600_APLL_EXT TO_REG(0x214) > +#define AST2600_MPLL_PARAM TO_REG(0x220) > #define AST2600_MPLL_EXT TO_REG(0x224) > +#define AST2600_EPLL_PARAM TO_REG(0x240) > #define AST2600_EPLL_EXT TO_REG(0x244) > +#define AST2600_DPLL_PARAM TO_REG(0x260) > +#define AST2600_DPLL_EXT TO_REG(0x264) > #define AST2600_CLK_SEL TO_REG(0x300) > #define AST2600_CLK_SEL2 TO_REG(0x304) > -#define AST2600_CLK_SEL3 TO_REG(0x310) > +#define AST2600_CLK_SEL3 TO_REG(0x308) Is it a bugfix? Otherwise this is annoying. Maybe: #define AST2600A1_CLK_SEL3 TO_REG(0x310) #define AST2600A3_CLK_SEL3 TO_REG(0x308) and... > +#define AST2600_CLK_SEL4 TO_REG(0x310) > +#define AST2600_CLK_SEL5 TO_REG(0x314) > #define AST2600_HW_STRAP1 TO_REG(0x500) > #define AST2600_HW_STRAP1_CLR TO_REG(0x504) > #define AST2600_HW_STRAP1_PROT TO_REG(0x508) > @@ -433,6 +443,8 @@ static uint32_t aspeed_silicon_revs[] = { > AST2500_A1_SILICON_REV, > AST2600_A0_SILICON_REV, > AST2600_A1_SILICON_REV, > + AST2600_A2_SILICON_REV, > + AST2600_A3_SILICON_REV, > }; > > bool is_supported_silicon_rev(uint32_t silicon_rev) > @@ -651,16 +663,26 @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = { > .valid.unaligned = false, > }; > > -static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = { > +static const uint32_t ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = { > [AST2600_SYS_RST_CTRL] = 0xF7C3FED8, > - [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC, > + [AST2600_SYS_RST_CTRL2] = 0x0DFFFFFC, > [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A, > [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, > + [AST2600_DEBUG_CTRL] = 0x00000FFF, > + [AST2600_DEBUG_CTRL2] = 0x000000FF, > [AST2600_SDRAM_HANDSHAKE] = 0x00000000, > - [AST2600_HPLL_PARAM] = 0x1000405F, > + [AST2600_HPLL_PARAM] = 0x1000408F, > + [AST2600_APLL_PARAM] = 0x1000405F, > + [AST2600_MPLL_PARAM] = 0x1008405F, > + [AST2600_EPLL_PARAM] = 0x1004077F, > + [AST2600_DPLL_PARAM] = 0x1078405F, > + [AST2600_CLK_SEL] = 0xF3940000, > + [AST2600_CLK_SEL2] = 0x00700000, > + [AST2600_CLK_SEL3] = 0x00000000, ... use AST2600A3_CLK_SEL3 here? So someone wanting the emulate the A1 doesn't get the nasty bug of having CLK_SEL3 misplaced. > + [AST2600_CLK_SEL4] = 0xF3F40000, > + [AST2600_CLK_SEL5] = 0x30000000, > [AST2600_CHIP_ID0] = 0x1234ABCD, > [AST2600_CHIP_ID1] = 0x88884444, > - > };
On 8/9/21 5:55 PM, Philippe Mathieu-Daudé wrote: > On 8/9/21 3:15 PM, Cédric Le Goater wrote: >> From: Joel Stanley <joel@jms.id.au> >> >> This is the latest revision of the ASPEED 2600 SoC. As there is no >> need to model multiple revisions of the same SoC for the moment, >> update the SCU AST2600 to model the A3 revision instead of the A1 and >> adapt the AST2600 SoC and machines. >> >> Reset values are taken from v8 of the datasheet. >> >> Signed-off-by: Joel Stanley <joel@jms.id.au> >> [ clg: - Introduced an Aspeed "ast2600-a3" SoC class >> - Commit log update ] >> Message-Id: <20210407171637.777743-21-clg@kaod.org> >> Signed-off-by: Cédric Le Goater <clg@kaod.org> >> Message-Id: <20210629142336.750058-3-clg@kaod.org> >> Signed-off-by: Cédric Le Goater <clg@kaod.org> >> --- >> include/hw/misc/aspeed_scu.h | 2 ++ >> hw/arm/aspeed.c | 6 +++--- >> hw/arm/aspeed_ast2600.c | 6 +++--- >> hw/misc/aspeed_scu.c | 36 +++++++++++++++++++++++++++++------- >> 4 files changed, 37 insertions(+), 13 deletions(-) > >> diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c >> index 40a38ebd8549..05edebedeb46 100644 >> --- a/hw/misc/aspeed_scu.c >> +++ b/hw/misc/aspeed_scu.c >> @@ -101,14 +101,24 @@ >> #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) >> #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) >> #define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94) >> +#define AST2600_DEBUG_CTRL TO_REG(0xC8) >> +#define AST2600_DEBUG_CTRL2 TO_REG(0xD8) >> #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100) >> #define AST2600_HPLL_PARAM TO_REG(0x200) >> #define AST2600_HPLL_EXT TO_REG(0x204) >> +#define AST2600_APLL_PARAM TO_REG(0x210) >> +#define AST2600_APLL_EXT TO_REG(0x214) >> +#define AST2600_MPLL_PARAM TO_REG(0x220) >> #define AST2600_MPLL_EXT TO_REG(0x224) >> +#define AST2600_EPLL_PARAM TO_REG(0x240) >> #define AST2600_EPLL_EXT TO_REG(0x244) >> +#define AST2600_DPLL_PARAM TO_REG(0x260) >> +#define AST2600_DPLL_EXT TO_REG(0x264) >> #define AST2600_CLK_SEL TO_REG(0x300) >> #define AST2600_CLK_SEL2 TO_REG(0x304) >> -#define AST2600_CLK_SEL3 TO_REG(0x310) >> +#define AST2600_CLK_SEL3 TO_REG(0x308) > > Is it a bugfix? Otherwise this is annoying. This is a bug in the model. These registers have the same layout on the A1. Thanks, C. > > Maybe: > > #define AST2600A1_CLK_SEL3 TO_REG(0x310) > #define AST2600A3_CLK_SEL3 TO_REG(0x308) > > and... > >> +#define AST2600_CLK_SEL4 TO_REG(0x310) >> +#define AST2600_CLK_SEL5 TO_REG(0x314) >> #define AST2600_HW_STRAP1 TO_REG(0x500) >> #define AST2600_HW_STRAP1_CLR TO_REG(0x504) >> #define AST2600_HW_STRAP1_PROT TO_REG(0x508) >> @@ -433,6 +443,8 @@ static uint32_t aspeed_silicon_revs[] = { >> AST2500_A1_SILICON_REV, >> AST2600_A0_SILICON_REV, >> AST2600_A1_SILICON_REV, >> + AST2600_A2_SILICON_REV, >> + AST2600_A3_SILICON_REV, >> }; >> >> bool is_supported_silicon_rev(uint32_t silicon_rev) >> @@ -651,16 +663,26 @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = { >> .valid.unaligned = false, >> }; >> >> -static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = { >> +static const uint32_t ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = { >> [AST2600_SYS_RST_CTRL] = 0xF7C3FED8, >> - [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC, >> + [AST2600_SYS_RST_CTRL2] = 0x0DFFFFFC, >> [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A, >> [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, >> + [AST2600_DEBUG_CTRL] = 0x00000FFF, >> + [AST2600_DEBUG_CTRL2] = 0x000000FF, >> [AST2600_SDRAM_HANDSHAKE] = 0x00000000, >> - [AST2600_HPLL_PARAM] = 0x1000405F, >> + [AST2600_HPLL_PARAM] = 0x1000408F, >> + [AST2600_APLL_PARAM] = 0x1000405F, >> + [AST2600_MPLL_PARAM] = 0x1008405F, >> + [AST2600_EPLL_PARAM] = 0x1004077F, >> + [AST2600_DPLL_PARAM] = 0x1078405F, >> + [AST2600_CLK_SEL] = 0xF3940000, >> + [AST2600_CLK_SEL2] = 0x00700000, >> + [AST2600_CLK_SEL3] = 0x00000000, > > ... use AST2600A3_CLK_SEL3 here? > > So someone wanting the emulate the A1 doesn't get > the nasty bug of having CLK_SEL3 misplaced. > >> + [AST2600_CLK_SEL4] = 0xF3F40000, >> + [AST2600_CLK_SEL5] = 0x30000000, >> [AST2600_CHIP_ID0] = 0x1234ABCD, >> [AST2600_CHIP_ID1] = 0x88884444, >> - >> };
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index d49bfb02fbdb..c14aff2bcbb5 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -43,6 +43,8 @@ struct AspeedSCUState { #define AST2500_A1_SILICON_REV 0x04010303U #define AST2600_A0_SILICON_REV 0x05000303U #define AST2600_A1_SILICON_REV 0x05010303U +#define AST2600_A2_SILICON_REV 0x05020303U +#define AST2600_A3_SILICON_REV 0x05030303U #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index c93941789fd4..1ea09584d1f6 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -997,7 +997,7 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; - amc->soc_name = "ast2600-a1"; + amc->soc_name = "ast2600-a3"; amc->hw_strap1 = AST2600_EVB_HW_STRAP1; amc->hw_strap2 = AST2600_EVB_HW_STRAP2; amc->fmc_model = "w25q512jv"; @@ -1017,7 +1017,7 @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; - amc->soc_name = "ast2600-a1"; + amc->soc_name = "ast2600-a3"; amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; amc->fmc_model = "mx66l1g45g"; @@ -1054,7 +1054,7 @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); mc->desc = "IBM Rainier BMC (Cortex-A7)"; - amc->soc_name = "ast2600-a1"; + amc->soc_name = "ast2600-a3"; amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; amc->fmc_model = "mx66l1g45g"; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index e3013128c670..8e1993790e6f 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -516,9 +516,9 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) dc->realize = aspeed_soc_ast2600_realize; - sc->name = "ast2600-a1"; + sc->name = "ast2600-a3"; sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); - sc->silicon_rev = AST2600_A1_SILICON_REV; + sc->silicon_rev = AST2600_A3_SILICON_REV; sc->sram_size = 0x16400; sc->spis_num = 2; sc->ehcis_num = 2; @@ -530,7 +530,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) } static const TypeInfo aspeed_soc_ast2600_type_info = { - .name = "ast2600-a1", + .name = "ast2600-a3", .parent = TYPE_ASPEED_SOC, .instance_size = sizeof(AspeedSoCState), .instance_init = aspeed_soc_ast2600_init, diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 40a38ebd8549..05edebedeb46 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -101,14 +101,24 @@ #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) #define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94) +#define AST2600_DEBUG_CTRL TO_REG(0xC8) +#define AST2600_DEBUG_CTRL2 TO_REG(0xD8) #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100) #define AST2600_HPLL_PARAM TO_REG(0x200) #define AST2600_HPLL_EXT TO_REG(0x204) +#define AST2600_APLL_PARAM TO_REG(0x210) +#define AST2600_APLL_EXT TO_REG(0x214) +#define AST2600_MPLL_PARAM TO_REG(0x220) #define AST2600_MPLL_EXT TO_REG(0x224) +#define AST2600_EPLL_PARAM TO_REG(0x240) #define AST2600_EPLL_EXT TO_REG(0x244) +#define AST2600_DPLL_PARAM TO_REG(0x260) +#define AST2600_DPLL_EXT TO_REG(0x264) #define AST2600_CLK_SEL TO_REG(0x300) #define AST2600_CLK_SEL2 TO_REG(0x304) -#define AST2600_CLK_SEL3 TO_REG(0x310) +#define AST2600_CLK_SEL3 TO_REG(0x308) +#define AST2600_CLK_SEL4 TO_REG(0x310) +#define AST2600_CLK_SEL5 TO_REG(0x314) #define AST2600_HW_STRAP1 TO_REG(0x500) #define AST2600_HW_STRAP1_CLR TO_REG(0x504) #define AST2600_HW_STRAP1_PROT TO_REG(0x508) @@ -433,6 +443,8 @@ static uint32_t aspeed_silicon_revs[] = { AST2500_A1_SILICON_REV, AST2600_A0_SILICON_REV, AST2600_A1_SILICON_REV, + AST2600_A2_SILICON_REV, + AST2600_A3_SILICON_REV, }; bool is_supported_silicon_rev(uint32_t silicon_rev) @@ -651,16 +663,26 @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = { .valid.unaligned = false, }; -static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = { +static const uint32_t ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = { [AST2600_SYS_RST_CTRL] = 0xF7C3FED8, - [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC, + [AST2600_SYS_RST_CTRL2] = 0x0DFFFFFC, [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A, [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, + [AST2600_DEBUG_CTRL] = 0x00000FFF, + [AST2600_DEBUG_CTRL2] = 0x000000FF, [AST2600_SDRAM_HANDSHAKE] = 0x00000000, - [AST2600_HPLL_PARAM] = 0x1000405F, + [AST2600_HPLL_PARAM] = 0x1000408F, + [AST2600_APLL_PARAM] = 0x1000405F, + [AST2600_MPLL_PARAM] = 0x1008405F, + [AST2600_EPLL_PARAM] = 0x1004077F, + [AST2600_DPLL_PARAM] = 0x1078405F, + [AST2600_CLK_SEL] = 0xF3940000, + [AST2600_CLK_SEL2] = 0x00700000, + [AST2600_CLK_SEL3] = 0x00000000, + [AST2600_CLK_SEL4] = 0xF3F40000, + [AST2600_CLK_SEL5] = 0x30000000, [AST2600_CHIP_ID0] = 0x1234ABCD, [AST2600_CHIP_ID1] = 0x88884444, - }; static void aspeed_ast2600_scu_reset(DeviceState *dev) @@ -675,7 +697,7 @@ static void aspeed_ast2600_scu_reset(DeviceState *dev) * of actual revision. QEMU and Linux only support A1 onwards so this is * sufficient. */ - s->regs[AST2600_SILICON_REV] = AST2600_A1_SILICON_REV; + s->regs[AST2600_SILICON_REV] = AST2600_A3_SILICON_REV; s->regs[AST2600_SILICON_REV2] = s->silicon_rev; s->regs[AST2600_HW_STRAP1] = s->hw_strap1; s->regs[AST2600_HW_STRAP2] = s->hw_strap2; @@ -689,7 +711,7 @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data) dc->desc = "ASPEED 2600 System Control Unit"; dc->reset = aspeed_ast2600_scu_reset; - asc->resets = ast2600_a1_resets; + asc->resets = ast2600_a3_resets; asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */ asc->apb_divider = 4; asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;