| Message ID | 09f57d55813f916578d1dd1e28bee3a621068bdd.1630319138.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/displayid: VESA vendor block and drm/i915 MSO use of it | expand |
On Mon, 30 Aug 2021, Jani Nikula <jani.nikula@intel.com> wrote: > The VESA Organization Vendor-Specific Data Block, defined in VESA > DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO) > stream count and segment pixel overlap. > > DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension, > describing how DisplayID sections may be embedded in EDID extension > blocks. DisplayID v2.0 does not have such a section, perhaps implying > that DisplayID v2.0 data should not be included in EDID extensions, but > rather in a "pure" DisplayID structure at its own DDC address pair > A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3. > > However, in practice, displays out in the field have embedded DisplayID > v2.0 data blocks in EDID extensions, including, in particular, some eDP > MSO displays, where a pure DisplayID structure is not available at all. > > Parse the MSO data from the DisplayID data block. Do it as part of > drm_add_display_info(), extending it to parse also DisplayID data to > avoid requiring extra calls to update the information. For reference, this is the EDID from a Lenovo ThinkPad X1 with eDP MSO display. AFAICT, the display does not respond on A4h/A5h at all, it only has the usual EDID at the usual DDC address. BR, Jani. edid-decode (hex): 00 ff ff ff ff ff ff 00 06 af 13 10 00 00 00 00 00 1c 01 04 a5 1c 13 78 02 ee 95 a3 54 4c 99 26 0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 d5 2b 68 50 40 e0 2c 50 18 10 3a 00 1c bd 10 00 00 18 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20 00 00 00 fe 00 42 31 33 35 51 41 4e 30 31 2e 30 20 0a 01 e1 70 20 08 06 00 7e 00 05 3a 02 92 00 20 61 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90 ---------------- Block 0, Base EDID: EDID Structure Version & Revision: 1.4 Vendor & Product Identification: Manufacturer: AUO Model: 4115 Made in: 2018 Basic Display Parameters & Features: Digital display Bits per primary color channel: 8 DisplayPort interface Maximum image size: 28 cm x 19 cm Gamma: 2.20 Supported color formats: RGB 4:4:4 First detailed timing includes the native pixel format and preferred refresh rate Color Characteristics: Red : 0.6396, 0.3300 Green: 0.2998, 0.5996 Blue : 0.1503, 0.0595 White: 0.3134, 0.3291 Established Timings I & II: none Standard Timings: none Detailed Timing Descriptors: DTD 1: 1128x1504 60.006 Hz 3:4 92.889 kHz 112.210 MHz (284 mm x 189 mm) Hfront 24 Hsync 16 Hback 40 Hpol N Vfront 3 Vsync 10 Vback 31 Vpol N Manufacturer-Specified Display Descriptor (0x0f): 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20 '............... ' Alphanumeric Data String: 'AUO' Alphanumeric Data String: 'B135QAN01.0 ' Extension blocks: 1 Checksum: 0xe1 ---------------- Block 1, DisplayID Extension Block: Version: 2.0 Extension Count: 0 Display Product Primary Use Case: Presentation display Vendor-Specific Data Block (VESA): Data Structure Type: eDP Default Colorspace and EOTF Handling: sRGB Number of Pixels in Hor Pix Cnt Overlapping an Adjacent Panel: 0 Multi-SST Operation: Two Streams (number of links shall be 2 or 4) Checksum: 0x61 Checksum: 0x90
On Mon, Aug 30, 2021 at 01:29:01PM +0300, Jani Nikula wrote: > The VESA Organization Vendor-Specific Data Block, defined in VESA > DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO) > stream count and segment pixel overlap. > > DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension, > describing how DisplayID sections may be embedded in EDID extension > blocks. DisplayID v2.0 does not have such a section, perhaps implying > that DisplayID v2.0 data should not be included in EDID extensions, but > rather in a "pure" DisplayID structure at its own DDC address pair > A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3. > > However, in practice, displays out in the field have embedded DisplayID > v2.0 data blocks in EDID extensions, including, in particular, some eDP > MSO displays, where a pure DisplayID structure is not available at all. > > Parse the MSO data from the DisplayID data block. Do it as part of > drm_add_display_info(), extending it to parse also DisplayID data to > avoid requiring extra calls to update the information. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/drm_edid.c | 63 +++++++++++++++++++++++++++++++++++++ > include/drm/drm_connector.h | 12 +++++++ > include/drm/drm_displayid.h | 11 +++++++ > 3 files changed, 86 insertions(+) > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > index 6325877c5fd6..7e8083068f3f 100644 > --- a/drivers/gpu/drm/drm_edid.c > +++ b/drivers/gpu/drm/drm_edid.c > @@ -28,6 +28,7 @@ > * DEALINGS IN THE SOFTWARE. > */ > > +#include <linux/bitfield.h> > #include <linux/hdmi.h> > #include <linux/i2c.h> > #include <linux/kernel.h> > @@ -5148,6 +5149,62 @@ void drm_get_monitor_range(struct drm_connector *connector, > info->monitor_range.max_vfreq); > } > > +static void drm_parse_vesa_mso_data(struct drm_connector *connector, > + const struct displayid_block *block) > +{ > + struct displayid_vesa_vendor_specific_block *vesa = > + (struct displayid_vesa_vendor_specific_block *)block; > + struct drm_display_info *info = &connector->display_info; > + > + if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { > + drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n"); > + return; > + } > + > + switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { > + default: > + drm_dbg_kms(connector->dev, "Reserved MSO mode value\n"); > + fallthrough; > + case 0: > + info->mso_stream_count = 0; > + break; > + case 1: > + info->mso_stream_count = 2; /* 2 or 4 links */ > + break; > + case 2: > + info->mso_stream_count = 4; /* 4 links */ > + break; > + } > + > + if (!info->mso_stream_count) { > + info->mso_pixel_overlap = 0; > + return; > + } > + > + info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); > + if (info->mso_pixel_overlap > 8) { > + drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n", > + info->mso_pixel_overlap); > + info->mso_pixel_overlap = 8; > + } > + > + drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n", > + info->mso_stream_count, info->mso_pixel_overlap); > +} > + > +static void drm_update_mso(struct drm_connector *connector, const struct edid *edid) > +{ > + const struct displayid_block *block; > + struct displayid_iter iter; > + > + displayid_iter_edid_begin(edid, &iter); > + displayid_iter_for_each(block, &iter) { > + if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) Don't we need to check the OUI to make sure the block is the right type? I don't have the v2 spec at hand atm, but I presume a vendor specific block could contain all kinds of different things? > + drm_parse_vesa_mso_data(connector, block); > + } > + displayid_iter_end(&iter); > +} > + > /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset > * all of the values which would have been set from EDID > */ > @@ -5171,6 +5228,9 @@ drm_reset_display_info(struct drm_connector *connector) > > info->non_desktop = 0; > memset(&info->monitor_range, 0, sizeof(info->monitor_range)); > + > + info->mso_stream_count = 0; > + info->mso_pixel_overlap = 0; > } > > u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) > @@ -5249,6 +5309,9 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi > info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; > if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) > info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; > + > + drm_update_mso(connector, edid); > + > return quirks; > } > > diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h > index 79fa34e5ccdb..379746d3266f 100644 > --- a/include/drm/drm_connector.h > +++ b/include/drm/drm_connector.h > @@ -590,6 +590,18 @@ struct drm_display_info { > * @monitor_range: Frequency range supported by monitor range descriptor > */ > struct drm_monitor_range_info monitor_range; > + > + /** > + * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from > + * the DisplayID VESA vendor block. 0 for conventional Single-Stream > + * Transport (SST), or 2 or 4 MSO streams. > + */ > + u8 mso_stream_count; > + > + /** > + * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels. > + */ > + u8 mso_pixel_overlap; > }; > > int drm_display_info_set_bus_formats(struct drm_display_info *info, > diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h > index 79771091771a..b18611e016a2 100644 > --- a/include/drm/drm_displayid.h > +++ b/include/drm/drm_displayid.h > @@ -23,6 +23,7 @@ > #define DRM_DISPLAYID_H > > #include <linux/types.h> > +#include <linux/bits.h> > > struct edid; > > @@ -126,6 +127,16 @@ struct displayid_detailed_timing_block { > struct displayid_detailed_timings_1 timings[]; > }; > > +#define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0) > +#define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5) > + > +struct displayid_vesa_vendor_specific_block { > + struct displayid_block base; > + u8 oui[3]; > + u8 data_structure_type; > + u8 mso; > +} __packed; > + > /* DisplayID iteration */ > struct displayid_iter { > const struct edid *edid; > -- > 2.20.1
On Mon, 30 Aug 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Mon, Aug 30, 2021 at 01:29:01PM +0300, Jani Nikula wrote: >> The VESA Organization Vendor-Specific Data Block, defined in VESA >> DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO) >> stream count and segment pixel overlap. >> >> DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension, >> describing how DisplayID sections may be embedded in EDID extension >> blocks. DisplayID v2.0 does not have such a section, perhaps implying >> that DisplayID v2.0 data should not be included in EDID extensions, but >> rather in a "pure" DisplayID structure at its own DDC address pair >> A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3. >> >> However, in practice, displays out in the field have embedded DisplayID >> v2.0 data blocks in EDID extensions, including, in particular, some eDP >> MSO displays, where a pure DisplayID structure is not available at all. >> >> Parse the MSO data from the DisplayID data block. Do it as part of >> drm_add_display_info(), extending it to parse also DisplayID data to >> avoid requiring extra calls to update the information. >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/drm_edid.c | 63 +++++++++++++++++++++++++++++++++++++ >> include/drm/drm_connector.h | 12 +++++++ >> include/drm/drm_displayid.h | 11 +++++++ >> 3 files changed, 86 insertions(+) >> >> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c >> index 6325877c5fd6..7e8083068f3f 100644 >> --- a/drivers/gpu/drm/drm_edid.c >> +++ b/drivers/gpu/drm/drm_edid.c >> @@ -28,6 +28,7 @@ >> * DEALINGS IN THE SOFTWARE. >> */ >> >> +#include <linux/bitfield.h> >> #include <linux/hdmi.h> >> #include <linux/i2c.h> >> #include <linux/kernel.h> >> @@ -5148,6 +5149,62 @@ void drm_get_monitor_range(struct drm_connector *connector, >> info->monitor_range.max_vfreq); >> } >> >> +static void drm_parse_vesa_mso_data(struct drm_connector *connector, >> + const struct displayid_block *block) >> +{ >> + struct displayid_vesa_vendor_specific_block *vesa = >> + (struct displayid_vesa_vendor_specific_block *)block; >> + struct drm_display_info *info = &connector->display_info; >> + >> + if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { >> + drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n"); >> + return; >> + } >> + >> + switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { >> + default: >> + drm_dbg_kms(connector->dev, "Reserved MSO mode value\n"); >> + fallthrough; >> + case 0: >> + info->mso_stream_count = 0; >> + break; >> + case 1: >> + info->mso_stream_count = 2; /* 2 or 4 links */ >> + break; >> + case 2: >> + info->mso_stream_count = 4; /* 4 links */ >> + break; >> + } >> + >> + if (!info->mso_stream_count) { >> + info->mso_pixel_overlap = 0; >> + return; >> + } >> + >> + info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); >> + if (info->mso_pixel_overlap > 8) { >> + drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n", >> + info->mso_pixel_overlap); >> + info->mso_pixel_overlap = 8; >> + } >> + >> + drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n", >> + info->mso_stream_count, info->mso_pixel_overlap); >> +} >> + >> +static void drm_update_mso(struct drm_connector *connector, const struct edid *edid) >> +{ >> + const struct displayid_block *block; >> + struct displayid_iter iter; >> + >> + displayid_iter_edid_begin(edid, &iter); >> + displayid_iter_for_each(block, &iter) { >> + if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) > > Don't we need to check the OUI to make sure the block is the right > type? I don't have the v2 spec at hand atm, but I presume a vendor > specific block could contain all kinds of different things? You're right. BR, Jani. > >> + drm_parse_vesa_mso_data(connector, block); >> + } >> + displayid_iter_end(&iter); >> +} >> + >> /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset >> * all of the values which would have been set from EDID >> */ >> @@ -5171,6 +5228,9 @@ drm_reset_display_info(struct drm_connector *connector) >> >> info->non_desktop = 0; >> memset(&info->monitor_range, 0, sizeof(info->monitor_range)); >> + >> + info->mso_stream_count = 0; >> + info->mso_pixel_overlap = 0; >> } >> >> u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) >> @@ -5249,6 +5309,9 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi >> info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; >> if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) >> info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; >> + >> + drm_update_mso(connector, edid); >> + >> return quirks; >> } >> >> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h >> index 79fa34e5ccdb..379746d3266f 100644 >> --- a/include/drm/drm_connector.h >> +++ b/include/drm/drm_connector.h >> @@ -590,6 +590,18 @@ struct drm_display_info { >> * @monitor_range: Frequency range supported by monitor range descriptor >> */ >> struct drm_monitor_range_info monitor_range; >> + >> + /** >> + * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from >> + * the DisplayID VESA vendor block. 0 for conventional Single-Stream >> + * Transport (SST), or 2 or 4 MSO streams. >> + */ >> + u8 mso_stream_count; >> + >> + /** >> + * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels. >> + */ >> + u8 mso_pixel_overlap; >> }; >> >> int drm_display_info_set_bus_formats(struct drm_display_info *info, >> diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h >> index 79771091771a..b18611e016a2 100644 >> --- a/include/drm/drm_displayid.h >> +++ b/include/drm/drm_displayid.h >> @@ -23,6 +23,7 @@ >> #define DRM_DISPLAYID_H >> >> #include <linux/types.h> >> +#include <linux/bits.h> >> >> struct edid; >> >> @@ -126,6 +127,16 @@ struct displayid_detailed_timing_block { >> struct displayid_detailed_timings_1 timings[]; >> }; >> >> +#define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0) >> +#define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5) >> + >> +struct displayid_vesa_vendor_specific_block { >> + struct displayid_block base; >> + u8 oui[3]; >> + u8 data_structure_type; >> + u8 mso; >> +} __packed; >> + >> /* DisplayID iteration */ >> struct displayid_iter { >> const struct edid *edid; >> -- >> 2.20.1
On Tue, 31 Aug 2021, Jani Nikula <jani.nikula@intel.com> wrote: > On Mon, 30 Aug 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: >> Don't we need to check the OUI to make sure the block is the right >> type? I don't have the v2 spec at hand atm, but I presume a vendor >> specific block could contain all kinds of different things? > > You're right. I resent the entire series because I added an OUI helper patch. I don't think patchwork could handle that as an in-reply-to update. https://patchwork.freedesktop.org/series/94161/ BR, Jani.
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 6325877c5fd6..7e8083068f3f 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -28,6 +28,7 @@ * DEALINGS IN THE SOFTWARE. */ +#include <linux/bitfield.h> #include <linux/hdmi.h> #include <linux/i2c.h> #include <linux/kernel.h> @@ -5148,6 +5149,62 @@ void drm_get_monitor_range(struct drm_connector *connector, info->monitor_range.max_vfreq); } +static void drm_parse_vesa_mso_data(struct drm_connector *connector, + const struct displayid_block *block) +{ + struct displayid_vesa_vendor_specific_block *vesa = + (struct displayid_vesa_vendor_specific_block *)block; + struct drm_display_info *info = &connector->display_info; + + if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { + drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n"); + return; + } + + switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { + default: + drm_dbg_kms(connector->dev, "Reserved MSO mode value\n"); + fallthrough; + case 0: + info->mso_stream_count = 0; + break; + case 1: + info->mso_stream_count = 2; /* 2 or 4 links */ + break; + case 2: + info->mso_stream_count = 4; /* 4 links */ + break; + } + + if (!info->mso_stream_count) { + info->mso_pixel_overlap = 0; + return; + } + + info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); + if (info->mso_pixel_overlap > 8) { + drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n", + info->mso_pixel_overlap); + info->mso_pixel_overlap = 8; + } + + drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n", + info->mso_stream_count, info->mso_pixel_overlap); +} + +static void drm_update_mso(struct drm_connector *connector, const struct edid *edid) +{ + const struct displayid_block *block; + struct displayid_iter iter; + + displayid_iter_edid_begin(edid, &iter); + displayid_iter_for_each(block, &iter) { + if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) + drm_parse_vesa_mso_data(connector, block); + } + displayid_iter_end(&iter); +} + /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset * all of the values which would have been set from EDID */ @@ -5171,6 +5228,9 @@ drm_reset_display_info(struct drm_connector *connector) info->non_desktop = 0; memset(&info->monitor_range, 0, sizeof(info->monitor_range)); + + info->mso_stream_count = 0; + info->mso_pixel_overlap = 0; } u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) @@ -5249,6 +5309,9 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; + + drm_update_mso(connector, edid); + return quirks; } diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index 79fa34e5ccdb..379746d3266f 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -590,6 +590,18 @@ struct drm_display_info { * @monitor_range: Frequency range supported by monitor range descriptor */ struct drm_monitor_range_info monitor_range; + + /** + * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from + * the DisplayID VESA vendor block. 0 for conventional Single-Stream + * Transport (SST), or 2 or 4 MSO streams. + */ + u8 mso_stream_count; + + /** + * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels. + */ + u8 mso_pixel_overlap; }; int drm_display_info_set_bus_formats(struct drm_display_info *info, diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h index 79771091771a..b18611e016a2 100644 --- a/include/drm/drm_displayid.h +++ b/include/drm/drm_displayid.h @@ -23,6 +23,7 @@ #define DRM_DISPLAYID_H #include <linux/types.h> +#include <linux/bits.h> struct edid; @@ -126,6 +127,16 @@ struct displayid_detailed_timing_block { struct displayid_detailed_timings_1 timings[]; }; +#define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0) +#define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5) + +struct displayid_vesa_vendor_specific_block { + struct displayid_block base; + u8 oui[3]; + u8 data_structure_type; + u8 mso; +} __packed; + /* DisplayID iteration */ struct displayid_iter { const struct edid *edid;
The VESA Organization Vendor-Specific Data Block, defined in VESA DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO) stream count and segment pixel overlap. DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension, describing how DisplayID sections may be embedded in EDID extension blocks. DisplayID v2.0 does not have such a section, perhaps implying that DisplayID v2.0 data should not be included in EDID extensions, but rather in a "pure" DisplayID structure at its own DDC address pair A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3. However, in practice, displays out in the field have embedded DisplayID v2.0 data blocks in EDID extensions, including, in particular, some eDP MSO displays, where a pure DisplayID structure is not available at all. Parse the MSO data from the DisplayID data block. Do it as part of drm_add_display_info(), extending it to parse also DisplayID data to avoid requiring extra calls to update the information. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/drm_edid.c | 63 +++++++++++++++++++++++++++++++++++++ include/drm/drm_connector.h | 12 +++++++ include/drm/drm_displayid.h | 11 +++++++ 3 files changed, 86 insertions(+)