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[0/2] riscv: improve unaligned memory accesses

Message ID 20210913121956.1776656-1-chenhuang5@huawei.com (mailing list archive)
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Series riscv: improve unaligned memory accesses | expand

Message

Chen Huang Sept. 13, 2021, 12:19 p.m. UTC 
The RISCV ISA can support unaligned memory accesses, so the patchset
selects HAVE_EFFICIENT_UNALIGNED_ACCESS and supports DCACHE_WORD_ACCESS
to improve the efficiency of unaligned memory accesses.

Chen Huang (2):
  riscv: Kconfig: select HAVE_EFFICIENT_UNALIGNED_ACCESS
  riscv: Support DCACHE_WORD_ACCESS

 arch/riscv/Kconfig                      |  2 ++
 arch/riscv/include/asm/word-at-a-time.h | 36 +++++++++++++++++++++++++
 2 files changed, 38 insertions(+)

Comments

Jisheng Zhang Sept. 15, 2021, 2:13 p.m. UTC | #1 
On Mon, 13 Sep 2021 12:19:54 +0000
Chen Huang <chenhuang5@huawei.com> wrote:

> The RISCV ISA can support unaligned memory accesses, so the patchset
> selects HAVE_EFFICIENT_UNALIGNED_ACCESS and supports DCACHE_WORD_ACCESS

NO, per the spec, "Even when misaligned loads and stores complete
successfully, these accesses might run extremely slowly depending on the
implementation". it's far away from "efficient"

> to improve the efficiency of unaligned memory accesses.
> 
> Chen Huang (2):
>   riscv: Kconfig: select HAVE_EFFICIENT_UNALIGNED_ACCESS
>   riscv: Support DCACHE_WORD_ACCESS
> 
>  arch/riscv/Kconfig                      |  2 ++
>  arch/riscv/include/asm/word-at-a-time.h | 36 +++++++++++++++++++++++++
>  2 files changed, 38 insertions(+)
>
Chen Huang Sept. 16, 2021, 2:54 a.m. UTC | #2 
Like ARM，powerpc and m68K，some CPUs don't support the unaligned memory access,
offer this as an option that CPU can choose it depending on its own design. I will
send v2 soon.

在 2021/9/15 22:13, Jisheng Zhang 写道:
> On Mon, 13 Sep 2021 12:19:54 +0000
> Chen Huang <chenhuang5@huawei.com> wrote:
> 
>> The RISCV ISA can support unaligned memory accesses, so the patchset
>> selects HAVE_EFFICIENT_UNALIGNED_ACCESS and supports DCACHE_WORD_ACCESS
> 
> NO, per the spec, "Even when misaligned loads and stores complete
> successfully, these accesses might run extremely slowly depending on the
> implementation". it's far away from "efficient"
> 
>> to improve the efficiency of unaligned memory accesses.
>>
>> Chen Huang (2):
>>   riscv: Kconfig: select HAVE_EFFICIENT_UNALIGNED_ACCESS
>>   riscv: Support DCACHE_WORD_ACCESS
>>
>>  arch/riscv/Kconfig                      |  2 ++
>>  arch/riscv/include/asm/word-at-a-time.h | 36 +++++++++++++++++++++++++
>>  2 files changed, 38 insertions(+)
>>
> 
> 
> .
>