| Message ID | 20210916130855.4054926-1-chenhuang5@huawei.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | riscv: improve unaligned memory accesses | expand |
On Thu, 16 Sep 2021 13:08:53 +0000 Chen Huang <chenhuang5@huawei.com> wrote: > The patchset improves RISCV unaligned memory accesses, selects > HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not > enabled and supports DCACHE_WORD_ACCESS to improve the efficiency > of unaligned memory accesses. > > If CPU don't support unaligned memory accesses for now, please > select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU > don't support unaligned memory accesses, I don't choose the > CONFIG for them. This will break unified kernel Image for riscv. Obviously, we will have two images for efficient unaligned access platforms and non-efficient unaligned access platforms. IMHO, we may need alternative mechanism or something else to dynamically enable related code path. Regards > > Changes since v1: > - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support > unaligned memory accesses, add an option for CPUs to choose it or not. > > Chen Huang (2): > riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS > riscv: Support DCACHE_WORD_ACCESS > > arch/riscv/Kconfig | 5 ++++ > arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++ > 2 files changed, 42 insertions(+) >
On 2021/9/17 22:14, Jisheng Zhang wrote: > On Thu, 16 Sep 2021 13:08:53 +0000 > Chen Huang <chenhuang5@huawei.com> wrote: > >> The patchset improves RISCV unaligned memory accesses, selects >> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not >> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency >> of unaligned memory accesses. >> >> If CPU don't support unaligned memory accesses for now, please >> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU >> don't support unaligned memory accesses, I don't choose the >> CONFIG for them. > This will break unified kernel Image for riscv. Obviously, we will have > two images for efficient unaligned access platforms and non-efficient > unaligned access platforms. IMHO, we may need alternative mechanism or > something else to dynamically enable related code path. it won't break unified kernel Image for riscv, if one SoC choose CPU_HAS_NO_UNALIGNED, the single Image won't support unaligned memory accesses, indeed, it depends on the CONFIG, and now, arm/powerpc/m68k has similar configuration. Yes, it could be an optimization via alternative mechanism or something else to dynamically enable related code path later. > > Regards > >> Changes since v1: >> - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support >> unaligned memory accesses, add an option for CPUs to choose it or not. >> >> Chen Huang (2): >> riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS >> riscv: Support DCACHE_WORD_ACCESS >> >> arch/riscv/Kconfig | 5 ++++ >> arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++ >> 2 files changed, 42 insertions(+) >> > > . >
On Sat, 18 Sep 2021 09:14:05 +0800 Kefeng Wang <wangkefeng.wang@huawei.com> wrote: > On 2021/9/17 22:14, Jisheng Zhang wrote: > > On Thu, 16 Sep 2021 13:08:53 +0000 > > Chen Huang <chenhuang5@huawei.com> wrote: > > > >> The patchset improves RISCV unaligned memory accesses, selects > >> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not > >> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency > >> of unaligned memory accesses. > >> > >> If CPU don't support unaligned memory accesses for now, please > >> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU > >> don't support unaligned memory accesses, I don't choose the > >> CONFIG for them. > > This will break unified kernel Image for riscv. Obviously, we will have > > two images for efficient unaligned access platforms and non-efficient > > unaligned access platforms. IMHO, we may need alternative mechanism or > > something else to dynamically enable related code path. > > it won't break unified kernel Image for riscv, if one SoC choose > > CPU_HAS_NO_UNALIGNED, the single Image won't support unaligned memory the "unified" means the kernel Image has to support all RV64GC or RV32GC SoCs. To make the Image works for both efficient unaligned access and inefficient unaligned access, I think we'd better make "inefficient unaligned access" default behavior, the use alternative etc. tech to patch related code path for efficient unaligned access. > > accesses, indeed, it depends on the CONFIG, and now, arm/powerpc/m68k has linux Distributions doesn't have enough background of which config options must be enabled. > > similar configuration. I have little knowledge of powerpc or m68k, but there are serveral different defconfig files for arm, for example multi_v7_defconfig and multi_v5_defconfig. The previous v7 version enables HAVE_EFFICIENT_UNALIGNED_ACCESS while the later v5 doesn't. Will you persuade riscv maintainers to accept one more defconfig file? Thanks > > Yes, it could be an optimization via alternative mechanism or something > else to > > dynamically enable related code path later. > > > > > Regards > > > >> Changes since v1: > >> - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support > >> unaligned memory accesses, add an option for CPUs to choose it or not. > >> > >> Chen Huang (2): > >> riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS > >> riscv: Support DCACHE_WORD_ACCESS > >> > >> arch/riscv/Kconfig | 5 ++++ > >> arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++ > >> 2 files changed, 42 insertions(+) > >> > > > > . > >
On Sat, 18 Sep 2021 07:17:13 PDT (-0700), jszhang3@mail.ustc.edu.cn wrote: > On Sat, 18 Sep 2021 09:14:05 +0800 > Kefeng Wang <wangkefeng.wang@huawei.com> wrote: > >> On 2021/9/17 22:14, Jisheng Zhang wrote: >> > On Thu, 16 Sep 2021 13:08:53 +0000 >> > Chen Huang <chenhuang5@huawei.com> wrote: >> > >> >> The patchset improves RISCV unaligned memory accesses, selects >> >> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not >> >> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency >> >> of unaligned memory accesses. >> >> >> >> If CPU don't support unaligned memory accesses for now, please >> >> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU >> >> don't support unaligned memory accesses, I don't choose the >> >> CONFIG for them. >> > This will break unified kernel Image for riscv. Obviously, we will have >> > two images for efficient unaligned access platforms and non-efficient >> > unaligned access platforms. IMHO, we may need alternative mechanism or >> > something else to dynamically enable related code path. >> >> it won't break unified kernel Image for riscv, if one SoC choose >> >> CPU_HAS_NO_UNALIGNED, the single Image won't support unaligned memory > > the "unified" means the kernel Image has to support all RV64GC or RV32GC SoCs. > To make the Image works for both efficient unaligned access and inefficient > unaligned access, I think we'd better make "inefficient unaligned access" > default behavior, the use alternative etc. tech to patch related code path > for efficient unaligned access. I agree, at least until we have a sufficient breadth of implementations to know whether efficient unaligned accesses are going to be possible. There was also a question about what exactly the C906 unaligned access handling looks like on GCC, as well. Do you guys have any sort of pipeline description? > > >> >> accesses, indeed, it depends on the CONFIG, and now, arm/powerpc/m68k has > > linux Distributions doesn't have enough background of which config options > must be enabled. I wouldn't be opposed to adding this as a Kconfig option, something along the lines of "tune for fast unaligned accesses" or whatever. I get that we're sort of just punting the problem to distros, but we could add a Kconfig.socs-like (though that is a mess, so we'd need something saner) tune target (which is maybe coupled to -mtune, as well?). That would a least let us give users the option of making this choice, and while it'd still likely be best to set this to slow unaligned accesse to start we may be able to more easily see what distros choose at this point. > >> >> similar configuration. > > I have little knowledge of powerpc or m68k, but there are serveral different > defconfig files for arm, for example multi_v7_defconfig and multi_v5_defconfig. > The previous v7 version enables HAVE_EFFICIENT_UNALIGNED_ACCESS while > the later v5 doesn't. Will you persuade riscv maintainers to accept one more > defconfig file? I'm not super worried about having more defconfigs, but I'm not really sure it's worth it for this option alone. > > Thanks > >> >> Yes, it could be an optimization via alternative mechanism or something >> else to >> >> dynamically enable related code path later. >> >> > >> > Regards >> > >> >> Changes since v1: >> >> - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support >> >> unaligned memory accesses, add an option for CPUs to choose it or not. >> >> >> >> Chen Huang (2): >> >> riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS >> >> riscv: Support DCACHE_WORD_ACCESS >> >> >> >> arch/riscv/Kconfig | 5 ++++ >> >> arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++ >> >> 2 files changed, 42 insertions(+) >> >> >> > >> > . >> >