| Message ID | 20210922180927.666273-4-git@xen0n.name (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | LoongArch64 port of QEMU TCG | expand |
On 9/22/21 20:09, WANG Xuerui wrote: > Support for all optional TCG ops are initially marked disabled; the bits > are to be set in individual commits later. > > Signed-off-by: WANG Xuerui <git@xen0n.name> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/loongarch64/tcg-target.h | 180 +++++++++++++++++++++++++++++++++++ > 1 file changed, 180 insertions(+) > create mode 100644 tcg/loongarch64/tcg-target.h > > diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h > new file mode 100644 > index 0000000000..0fd9b61e6d > --- /dev/null > +++ b/tcg/loongarch64/tcg-target.h > @@ -0,0 +1,180 @@ > +/* > + * Tiny Code Generator for QEMU > + * > + * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> > + * > + * Based on tcg/riscv/tcg-target.h > + * > + * Copyright (c) 2018 SiFive, Inc I thought you could drop this line. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#ifndef LOONGARCH_TCG_TARGET_H > +#define LOONGARCH_TCG_TARGET_H > + > +/* > + * Loongson removed the (incomplete) 32-bit support from kernel and toolchain > + * for the initial upstreaming of this architecture, so don't bother and just > + * support the LP64 ABI for now. > + */ > +#if defined(__loongarch64) > +# define TCG_TARGET_REG_BITS 64 > +#else > +# error unsupported LoongArch register size > +#endif > + > +#define TCG_TARGET_INSN_UNIT_SIZE 4 > +#define TCG_TARGET_NB_REGS 32 > +#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) Is this SIZE_MAX? > + > +typedef enum { > + TCG_REG_ZERO, > + TCG_REG_RA, > + TCG_REG_TP, > + TCG_REG_SP, > + TCG_REG_A0, > + TCG_REG_A1, > + TCG_REG_A2, > + TCG_REG_A3, > + TCG_REG_A4, > + TCG_REG_A5, > + TCG_REG_A6, > + TCG_REG_A7, > + TCG_REG_T0, > + TCG_REG_T1, > + TCG_REG_T2, > + TCG_REG_T3, > + TCG_REG_T4, > + TCG_REG_T5, > + TCG_REG_T6, > + TCG_REG_T7, > + TCG_REG_T8, > + TCG_REG_RESERVED, > + TCG_REG_S9, > + TCG_REG_S0, > + TCG_REG_S1, > + TCG_REG_S2, > + TCG_REG_S3, > + TCG_REG_S4, > + TCG_REG_S5, > + TCG_REG_S6, > + TCG_REG_S7, > + TCG_REG_S8, Here could go: TCG_TARGET_NB_REGS, > + > + /* aliases */ > + TCG_AREG0 = TCG_REG_S0, > + TCG_REG_TMP0 = TCG_REG_T8, > + TCG_REG_TMP1 = TCG_REG_T7, > + TCG_REG_TMP2 = TCG_REG_T6, > +} TCGReg; Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Hi Philippe, On 9/23/21 02:34, Philippe Mathieu-Daudé wrote: > On 9/22/21 20:09, WANG Xuerui wrote: >> Support for all optional TCG ops are initially marked disabled; the bits >> are to be set in individual commits later. >> >> Signed-off-by: WANG Xuerui <git@xen0n.name> >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> >> --- >> tcg/loongarch64/tcg-target.h | 180 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 180 insertions(+) >> create mode 100644 tcg/loongarch64/tcg-target.h >> >> diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h >> new file mode 100644 >> index 0000000000..0fd9b61e6d >> --- /dev/null >> +++ b/tcg/loongarch64/tcg-target.h >> @@ -0,0 +1,180 @@ >> +/* >> + * Tiny Code Generator for QEMU >> + * >> + * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> >> + * >> + * Based on tcg/riscv/tcg-target.h >> + * >> + * Copyright (c) 2018 SiFive, Inc > > I thought you could drop this line. That's the original file's copyright line, and I always thought dropping it in derivative files wouldn't be nice? > >> + * >> + * Permission is hereby granted, free of charge, to any person >> obtaining a copy >> + * of this software and associated documentation files (the >> "Software"), to deal >> + * in the Software without restriction, including without limitation >> the rights >> + * to use, copy, modify, merge, publish, distribute, sublicense, >> and/or sell >> + * copies of the Software, and to permit persons to whom the >> Software is >> + * furnished to do so, subject to the following conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> included in >> + * all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> EXPRESS OR >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF >> MERCHANTABILITY, >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT >> SHALL >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES >> OR OTHER >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >> ARISING FROM, >> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER >> DEALINGS IN >> + * THE SOFTWARE. >> + */ >> + >> +#ifndef LOONGARCH_TCG_TARGET_H >> +#define LOONGARCH_TCG_TARGET_H >> + >> +/* >> + * Loongson removed the (incomplete) 32-bit support from kernel and >> toolchain >> + * for the initial upstreaming of this architecture, so don't bother >> and just >> + * support the LP64 ABI for now. >> + */ >> +#if defined(__loongarch64) >> +# define TCG_TARGET_REG_BITS 64 >> +#else >> +# error unsupported LoongArch register size >> +#endif >> + >> +#define TCG_TARGET_INSN_UNIT_SIZE 4 >> +#define TCG_TARGET_NB_REGS 32 >> +#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) > > Is this SIZE_MAX? I just did a quick grep across the tcg ports and found little similarity so far... aarch64 (2 * GiB) arm UINT32_MAX i386 (2 * GiB) i386 UINT32_MAX loongarch64 ((size_t)-1) mips (128 * MiB) ppc (2 * GiB) ppc (32 * MiB) riscv ((size_t)-1) s390 (3 * GiB) sparc (2 * GiB) tci ((size_t)-1) In that case, I think maybe SIZE_MAX would indeed be better for readability, so I'm going to change that... > >> + >> +typedef enum { >> + TCG_REG_ZERO, >> + TCG_REG_RA, >> + TCG_REG_TP, >> + TCG_REG_SP, >> + TCG_REG_A0, >> + TCG_REG_A1, >> + TCG_REG_A2, >> + TCG_REG_A3, >> + TCG_REG_A4, >> + TCG_REG_A5, >> + TCG_REG_A6, >> + TCG_REG_A7, >> + TCG_REG_T0, >> + TCG_REG_T1, >> + TCG_REG_T2, >> + TCG_REG_T3, >> + TCG_REG_T4, >> + TCG_REG_T5, >> + TCG_REG_T6, >> + TCG_REG_T7, >> + TCG_REG_T8, >> + TCG_REG_RESERVED, >> + TCG_REG_S9, >> + TCG_REG_S0, >> + TCG_REG_S1, >> + TCG_REG_S2, >> + TCG_REG_S3, >> + TCG_REG_S4, >> + TCG_REG_S5, >> + TCG_REG_S6, >> + TCG_REG_S7, >> + TCG_REG_S8, > > Here could go: > > TCG_TARGET_NB_REGS, Good idea, something no other TCG ports has done... maybe we could refactor them all to avoid a little redundancy. I'll do this in v4. > >> + >> + /* aliases */ >> + TCG_AREG0 = TCG_REG_S0, >> + TCG_REG_TMP0 = TCG_REG_T8, >> + TCG_REG_TMP1 = TCG_REG_T7, >> + TCG_REG_TMP2 = TCG_REG_T6, >> +} TCGReg; > > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
On 9/22/21 11:34 AM, Philippe Mathieu-Daudé wrote: > > Here could go: > > TCG_TARGET_NB_REGS, Not a fan of putting NFOO in the enumeration. It interferes with -Wenum stuff. r~
On 9/22/21 20:58, Richard Henderson wrote: > On 9/22/21 11:34 AM, Philippe Mathieu-Daudé wrote: >> >> Here could go: >> >> TCG_TARGET_NB_REGS, > > Not a fan of putting NFOO in the enumeration. > It interferes with -Wenum stuff. Oh good point... TIL :)
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h new file mode 100644 index 0000000000..0fd9b61e6d --- /dev/null +++ b/tcg/loongarch64/tcg-target.h @@ -0,0 +1,180 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> + * + * Based on tcg/riscv/tcg-target.h + * + * Copyright (c) 2018 SiFive, Inc + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef LOONGARCH_TCG_TARGET_H +#define LOONGARCH_TCG_TARGET_H + +/* + * Loongson removed the (incomplete) 32-bit support from kernel and toolchain + * for the initial upstreaming of this architecture, so don't bother and just + * support the LP64 ABI for now. + */ +#if defined(__loongarch64) +# define TCG_TARGET_REG_BITS 64 +#else +# error unsupported LoongArch register size +#endif + +#define TCG_TARGET_INSN_UNIT_SIZE 4 +#define TCG_TARGET_NB_REGS 32 +#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) + +typedef enum { + TCG_REG_ZERO, + TCG_REG_RA, + TCG_REG_TP, + TCG_REG_SP, + TCG_REG_A0, + TCG_REG_A1, + TCG_REG_A2, + TCG_REG_A3, + TCG_REG_A4, + TCG_REG_A5, + TCG_REG_A6, + TCG_REG_A7, + TCG_REG_T0, + TCG_REG_T1, + TCG_REG_T2, + TCG_REG_T3, + TCG_REG_T4, + TCG_REG_T5, + TCG_REG_T6, + TCG_REG_T7, + TCG_REG_T8, + TCG_REG_RESERVED, + TCG_REG_S9, + TCG_REG_S0, + TCG_REG_S1, + TCG_REG_S2, + TCG_REG_S3, + TCG_REG_S4, + TCG_REG_S5, + TCG_REG_S6, + TCG_REG_S7, + TCG_REG_S8, + + /* aliases */ + TCG_AREG0 = TCG_REG_S0, + TCG_REG_TMP0 = TCG_REG_T8, + TCG_REG_TMP1 = TCG_REG_T7, + TCG_REG_TMP2 = TCG_REG_T6, +} TCGReg; + +/* used for function call generation */ +#define TCG_REG_CALL_STACK TCG_REG_SP +#define TCG_TARGET_STACK_ALIGN 16 +#define TCG_TARGET_CALL_ALIGN_ARGS 1 +#define TCG_TARGET_CALL_STACK_OFFSET 0 + +/* optional instructions */ +#define TCG_TARGET_HAS_movcond_i32 0 +#define TCG_TARGET_HAS_div_i32 0 +#define TCG_TARGET_HAS_rem_i32 0 +#define TCG_TARGET_HAS_div2_i32 0 +#define TCG_TARGET_HAS_rot_i32 0 +#define TCG_TARGET_HAS_deposit_i32 0 +#define TCG_TARGET_HAS_extract_i32 0 +#define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract2_i32 0 +#define TCG_TARGET_HAS_add2_i32 0 +#define TCG_TARGET_HAS_sub2_i32 0 +#define TCG_TARGET_HAS_mulu2_i32 0 +#define TCG_TARGET_HAS_muls2_i32 0 +#define TCG_TARGET_HAS_muluh_i32 0 +#define TCG_TARGET_HAS_mulsh_i32 0 +#define TCG_TARGET_HAS_ext8s_i32 0 +#define TCG_TARGET_HAS_ext16s_i32 0 +#define TCG_TARGET_HAS_ext8u_i32 0 +#define TCG_TARGET_HAS_ext16u_i32 0 +#define TCG_TARGET_HAS_bswap16_i32 0 +#define TCG_TARGET_HAS_bswap32_i32 0 +#define TCG_TARGET_HAS_not_i32 0 +#define TCG_TARGET_HAS_neg_i32 0 +#define TCG_TARGET_HAS_andc_i32 0 +#define TCG_TARGET_HAS_orc_i32 0 +#define TCG_TARGET_HAS_eqv_i32 0 +#define TCG_TARGET_HAS_nand_i32 0 +#define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_clz_i32 0 +#define TCG_TARGET_HAS_ctz_i32 0 +#define TCG_TARGET_HAS_ctpop_i32 0 +#define TCG_TARGET_HAS_direct_jump 0 +#define TCG_TARGET_HAS_brcond2 0 +#define TCG_TARGET_HAS_setcond2 0 +#define TCG_TARGET_HAS_qemu_st8_i32 0 + +/* 64-bit operations */ +#define TCG_TARGET_HAS_movcond_i64 0 +#define TCG_TARGET_HAS_div_i64 0 +#define TCG_TARGET_HAS_rem_i64 0 +#define TCG_TARGET_HAS_div2_i64 0 +#define TCG_TARGET_HAS_rot_i64 0 +#define TCG_TARGET_HAS_deposit_i64 0 +#define TCG_TARGET_HAS_extract_i64 0 +#define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract2_i64 0 +#define TCG_TARGET_HAS_extrl_i64_i32 0 +#define TCG_TARGET_HAS_extrh_i64_i32 0 +#define TCG_TARGET_HAS_ext8s_i64 0 +#define TCG_TARGET_HAS_ext16s_i64 0 +#define TCG_TARGET_HAS_ext32s_i64 0 +#define TCG_TARGET_HAS_ext8u_i64 0 +#define TCG_TARGET_HAS_ext16u_i64 0 +#define TCG_TARGET_HAS_ext32u_i64 0 +#define TCG_TARGET_HAS_bswap16_i64 0 +#define TCG_TARGET_HAS_bswap32_i64 0 +#define TCG_TARGET_HAS_bswap64_i64 0 +#define TCG_TARGET_HAS_not_i64 0 +#define TCG_TARGET_HAS_neg_i64 0 +#define TCG_TARGET_HAS_andc_i64 0 +#define TCG_TARGET_HAS_orc_i64 0 +#define TCG_TARGET_HAS_eqv_i64 0 +#define TCG_TARGET_HAS_nand_i64 0 +#define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_clz_i64 0 +#define TCG_TARGET_HAS_ctz_i64 0 +#define TCG_TARGET_HAS_ctpop_i64 0 +#define TCG_TARGET_HAS_add2_i64 0 +#define TCG_TARGET_HAS_sub2_i64 0 +#define TCG_TARGET_HAS_mulu2_i64 0 +#define TCG_TARGET_HAS_muls2_i64 0 +#define TCG_TARGET_HAS_muluh_i64 0 +#define TCG_TARGET_HAS_mulsh_i64 0 + +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); + +#define TCG_TARGET_DEFAULT_MO (0) + +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif + +#define TCG_TARGET_HAS_MEMORY_BSWAP 0 + +#endif /* LOONGARCH_TCG_TARGET_H */