| Message ID | 20220111142054.18733-1-nikita.shubin@maquefel.me (mailing list archive) |
|---|---|
| Headers | show |
| Series | perf tools: Add 'm' event modifier for counting | expand |
On 11 Jan 2022, at 14:20, Nikita Shubin <nikita.shubin@maquefel.me> wrote: > > From: Nikita Shubin <n.shubin@yadro.com> > > This patch is a proposal to add Machine Mode modifier that is currently > available only for RISC-V for perf tool. > > We don't currently have a level that is lower than kernel, so i don't > see we can reuse something existing for this purpose. > > The exclude_machine bit seems harmless to as no one will proccess it apart > of riscv. Armv8 has equivalent bits in PMEVTYPER<n>_EL0 and PMCCFILTR_EL0 for EL-based filtering, which includes filtering EL3. Jess > Patch depends on Atish Patra PMU series: > https://lwn.net/Articles/879905/ > + some modifications to pass execlude event to SBI PMU extension > > Tested with qemu. > > Nikita Shubin (1): > perf tools: Add 'm' event modifier for counting machine > > include/uapi/linux/perf_event.h | 3 ++- > tools/include/uapi/linux/perf_event.h | 3 ++- > tools/perf/Documentation/perf-list.txt | 1 + > tools/perf/tests/parse-events.c | 18 ++++++++++++++++++ > tools/perf/util/evsel.c | 4 +++- > tools/perf/util/parse-events.c | 18 +++++++++++++----- > tools/perf/util/parse-events.l | 2 +- > 7 files changed, 40 insertions(+), 9 deletions(-) > > -- > 2.31.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Tue, Jan 11, 2022 at 6:29 AM Jessica Clarke <jrtc27@jrtc27.com> wrote: > > On 11 Jan 2022, at 14:20, Nikita Shubin <nikita.shubin@maquefel.me> wrote: > > > > From: Nikita Shubin <n.shubin@yadro.com> > > > > This patch is a proposal to add Machine Mode modifier that is currently > > available only for RISC-V for perf tool. > > > > We don't currently have a level that is lower than kernel, so i don't > > see we can reuse something existing for this purpose. > > Thanks for a quick turnaround with a working patch!! However, the use case can be applied to other arch as well. It would be good to classify this as excluding "firmware" events instead of machine mode which is a RISC-V terminology. Ofcourse, the current documentation should indicate that this option is only useful for RISC-V right now. I would like to understand if this idea is appealing to the broader community. > > The exclude_machine bit seems harmless to as no one will proccess it apart > > of riscv. > > Armv8 has equivalent bits in PMEVTYPER<n>_EL0 and PMCCFILTR_EL0 for > EL-based filtering, which includes filtering EL3. > > Jess > > > Patch depends on Atish Patra PMU series: > > https://lwn.net/Articles/879905/ > > + some modifications to pass execlude event to SBI PMU extension > > > > Tested with qemu. > > > > Nikita Shubin (1): > > perf tools: Add 'm' event modifier for counting machine > > > > include/uapi/linux/perf_event.h | 3 ++- > > tools/include/uapi/linux/perf_event.h | 3 ++- > > tools/perf/Documentation/perf-list.txt | 1 + > > tools/perf/tests/parse-events.c | 18 ++++++++++++++++++ > > tools/perf/util/evsel.c | 4 +++- > > tools/perf/util/parse-events.c | 18 +++++++++++++----- > > tools/perf/util/parse-events.l | 2 +- > > 7 files changed, 40 insertions(+), 9 deletions(-) > > > > -- > > 2.31.1 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Tue, 11 Jan 2022 14:29:15 +0000 Jessica Clarke <jrtc27@jrtc27.com> wrote: Hello Jessica! > On 11 Jan 2022, at 14:20, Nikita Shubin <nikita.shubin@maquefel.me> > wrote: > > > > From: Nikita Shubin <n.shubin@yadro.com> > > > > This patch is a proposal to add Machine Mode modifier that is > > currently available only for RISC-V for perf tool. > > > > We don't currently have a level that is lower than kernel, so i > > don't see we can reuse something existing for this purpose. > > > > The exclude_machine bit seems harmless to as no one will proccess > > it apart of riscv. > > Armv8 has equivalent bits in PMEVTYPER<n>_EL0 and PMCCFILTR_EL0 for > EL-based filtering, which includes filtering EL3. > Thank your for your tip, i ll study it and see if this is a good way to go. > Jess > > > Patch depends on Atish Patra PMU series: > > https://lwn.net/Articles/879905/ > > + some modifications to pass execlude event to SBI PMU extension > > > > Tested with qemu. > > > > Nikita Shubin (1): > > perf tools: Add 'm' event modifier for counting machine > > > > include/uapi/linux/perf_event.h | 3 ++- > > tools/include/uapi/linux/perf_event.h | 3 ++- > > tools/perf/Documentation/perf-list.txt | 1 + > > tools/perf/tests/parse-events.c | 18 ++++++++++++++++++ > > tools/perf/util/evsel.c | 4 +++- > > tools/perf/util/parse-events.c | 18 +++++++++++++----- > > tools/perf/util/parse-events.l | 2 +- > > 7 files changed, 40 insertions(+), 9 deletions(-) > > > > -- > > 2.31.1 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv >
Hello Atish! On Tue, 11 Jan 2022 10:45:56 -0800 Atish Patra <atishp@atishpatra.org> wrote: > On Tue, Jan 11, 2022 at 6:29 AM Jessica Clarke <jrtc27@jrtc27.com> > wrote: > > > > On 11 Jan 2022, at 14:20, Nikita Shubin <nikita.shubin@maquefel.me> > > wrote: > > > > > > From: Nikita Shubin <n.shubin@yadro.com> > > > > > > This patch is a proposal to add Machine Mode modifier that is > > > currently available only for RISC-V for perf tool. > > > > > > We don't currently have a level that is lower than kernel, so i > > > don't see we can reuse something existing for this purpose. > > > > > Thanks for a quick turnaround with a working patch!! > Nothing please - your RISC-V PMU series as well as your work on sscofpmf extension are great, so i am glad i can help you with that. > However, the use case can be applied to other arch as well. It would > be good to classify this > as excluding "firmware" events instead of machine mode which is a > RISC-V terminology. That's a bit confusing cause, "firmware" resides in M-Mode in RISC-V case and it's another level of privilege, i don't think it's possible to exclude firmware that is on the same level as kernel. For example we have PSCI in ARM, which falls in "firmware" category, in my option, but we can't distinguish from other stuff on same privilege level. > Ofcourse, the current documentation should indicate that this option > is only useful > for RISC-V right now. > > I would like to understand if this idea is appealing to the broader > community. Yes - i would like to hear if adding event modifier is a way to go or not. > > > > The exclude_machine bit seems harmless to as no one will proccess > > > it apart of riscv. > > > > Armv8 has equivalent bits in PMEVTYPER<n>_EL0 and PMCCFILTR_EL0 for > > EL-based filtering, which includes filtering EL3. > > > > Jess > > > > > Patch depends on Atish Patra PMU series: > > > https://lwn.net/Articles/879905/ > > > + some modifications to pass execlude event to SBI PMU extension > > > > > > Tested with qemu. > > > > > > Nikita Shubin (1): > > > perf tools: Add 'm' event modifier for counting machine > > > > > > include/uapi/linux/perf_event.h | 3 ++- > > > tools/include/uapi/linux/perf_event.h | 3 ++- > > > tools/perf/Documentation/perf-list.txt | 1 + > > > tools/perf/tests/parse-events.c | 18 ++++++++++++++++++ > > > tools/perf/util/evsel.c | 4 +++- > > > tools/perf/util/parse-events.c | 18 +++++++++++++----- > > > tools/perf/util/parse-events.l | 2 +- > > > 7 files changed, 40 insertions(+), 9 deletions(-) > > > > > > -- > > > 2.31.1 > > > > > > > > > _______________________________________________ > > > linux-riscv mailing list > > > linux-riscv@lists.infradead.org > > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > >
From: Nikita Shubin <n.shubin@yadro.com> This patch is a proposal to add Machine Mode modifier that is currently available only for RISC-V for perf tool. We don't currently have a level that is lower than kernel, so i don't see we can reuse something existing for this purpose. The exclude_machine bit seems harmless to as no one will proccess it apart of riscv. Patch depends on Atish Patra PMU series: https://lwn.net/Articles/879905/ + some modifications to pass execlude event to SBI PMU extension Tested with qemu. Nikita Shubin (1): perf tools: Add 'm' event modifier for counting machine include/uapi/linux/perf_event.h | 3 ++- tools/include/uapi/linux/perf_event.h | 3 ++- tools/perf/Documentation/perf-list.txt | 1 + tools/perf/tests/parse-events.c | 18 ++++++++++++++++++ tools/perf/util/evsel.c | 4 +++- tools/perf/util/parse-events.c | 18 +++++++++++++----- tools/perf/util/parse-events.l | 2 +- 7 files changed, 40 insertions(+), 9 deletions(-)