| Message ID | 20220118111736.454150-3-apatel@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Improve RISC-V spike machine bios support | expand |
On Tue, Jan 18, 2022 at 9:18 PM Anup Patel <apatel@ventanamicro.com> wrote: > > Now that RISC-V Spike machine can use BIN BIOS images, we remove > the macros used for ELF BIOS image names. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/spike.c | 4 ++-- > include/hw/riscv/boot.h | 2 -- > 2 files changed, 2 insertions(+), 4 deletions(-) > > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 597df4c288..d059a67f9b 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -260,11 +260,11 @@ static void spike_board_init(MachineState *machine) > */ > if (riscv_is_32bit(&s->soc[0])) { > firmware_end_addr = riscv_find_and_load_firmware(machine, > - RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base, > + RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base, > htif_symbol_callback); > } else { > firmware_end_addr = riscv_find_and_load_firmware(machine, > - RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base, > + RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base, > htif_symbol_callback); > } > > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index baff11dd8a..d486392cd0 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -25,9 +25,7 @@ > #include "hw/riscv/riscv_hart.h" > > #define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin" > -#define RISCV32_BIOS_ELF "opensbi-riscv32-generic-fw_dynamic.elf" > #define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin" > -#define RISCV64_BIOS_ELF "opensbi-riscv64-generic-fw_dynamic.elf" > > bool riscv_is_32bit(RISCVHartArrayState *harts); > > -- > 2.25.1 > >
On Tue, Jan 18, 2022 at 7:18 PM Anup Patel <apatel@ventanamicro.com> wrote: > > Now that RISC-V Spike machine can use BIN BIOS images, we remove > the macros used for ELF BIOS image names. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > hw/riscv/spike.c | 4 ++-- > include/hw/riscv/boot.h | 2 -- > 2 files changed, 2 insertions(+), 4 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 597df4c288..d059a67f9b 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -260,11 +260,11 @@ static void spike_board_init(MachineState *machine) */ if (riscv_is_32bit(&s->soc[0])) { firmware_end_addr = riscv_find_and_load_firmware(machine, - RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base, + RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base, htif_symbol_callback); } else { firmware_end_addr = riscv_find_and_load_firmware(machine, - RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base, + RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base, htif_symbol_callback); } diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index baff11dd8a..d486392cd0 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -25,9 +25,7 @@ #include "hw/riscv/riscv_hart.h" #define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin" -#define RISCV32_BIOS_ELF "opensbi-riscv32-generic-fw_dynamic.elf" #define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin" -#define RISCV64_BIOS_ELF "opensbi-riscv64-generic-fw_dynamic.elf" bool riscv_is_32bit(RISCVHartArrayState *harts);
Now that RISC-V Spike machine can use BIN BIOS images, we remove the macros used for ELF BIOS image names. Signed-off-by: Anup Patel <apatel@ventanamicro.com> --- hw/riscv/spike.c | 4 ++-- include/hw/riscv/boot.h | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-)