[2/2] xen/x86: detect support for extended destination ID

Commit Message

Roger Pau Monne Jan. 20, 2022, 3:25 p.m. UTC

Xen allows the usage of some previously reserved bits in the IO-APIC
RTE and the MSI address fields in order to store high bits for the
target APIC ID. Such feature is already implemented by QEMU/KVM and
HyperV, so in order to enable it just add the handler that checks for
it's presence.

Signed-off-by: Roger Pau Monné <[e-mail]>
---
Must not be applied until the public headers are changed in Xen.
---
Cc: Boris Ostrovsky <[e-mail]>
Cc: Juergen Gross <[e-mail]>
Cc: Stefano Stabellini <[e-mail]>
Cc: Thomas Gleixner <[e-mail]>
Cc: Ingo Molnar <[e-mail]>
Cc: Borislav Petkov <[e-mail]>
Cc: Dave Hansen <[e-mail]>
Cc: [e-mail]
Cc: "H. Peter Anvin" <[e-mail]>
Cc: [e-mail]
---
 arch/x86/include/asm/xen/cpuid.h | 7 +++++++
 arch/x86/xen/enlighten_hvm.c     | 6 ++++++
 2 files changed, 13 insertions(+)

Comments

Jürgen Groß Feb. 7, 2022, 9:03 a.m. UTC | #1

On 20.01.22 16:25, Roger Pau Monne wrote:
> Xen allows the usage of some previously reserved bits in the IO-APIC
> RTE and the MSI address fields in order to store high bits for the
> target APIC ID. Such feature is already implemented by QEMU/KVM and
> HyperV, so in order to enable it just add the handler that checks for
> it's presence.
> 
> Signed-off-by: Roger Pau Monné <[e-mail]>

Reviewed-by: Juergen Gross <[e-mail]>


Juergen

Patch

diff --git a/arch/x86/include/asm/xen/cpuid.h b/arch/x86/include/asm/xen/cpuid.h
index a9630104f1c4..78e667a31d6c 100644
--- a/arch/x86/include/asm/xen/cpuid.h
+++ b/arch/x86/include/asm/xen/cpuid.h
@@ -100,6 +100,13 @@ 
 /* Memory mapped from other domains has valid IOMMU entries */
 #define XEN_HVM_CPUID_IOMMU_MAPPINGS   (1u << 2)
 #define XEN_HVM_CPUID_VCPU_ID_PRESENT  (1u << 3) /* vcpu id is present in EBX */
+#define XEN_HVM_CPUID_DOMID_PRESENT    (1u << 4) /* domid is present in ECX */
+/*
+ * Bits 55:49 from the IO-APIC RTE and bits 11:5 from the MSI address can be
+ * used to store high bits for the Destination ID. This expands the Destination
+ * ID field from 8 to 15 bits, allowing to target APIC IDs up 32768.
+ */
+#define XEN_HVM_CPUID_EXT_DEST_ID      (1u << 5)
 
 /*
  * Leaf 6 (0x40000x05)
diff --git a/arch/x86/xen/enlighten_hvm.c b/arch/x86/xen/enlighten_hvm.c
index ab8171cbee23..0c5b0ee3a02a 100644
--- a/arch/x86/xen/enlighten_hvm.c
+++ b/arch/x86/xen/enlighten_hvm.c
@@ -254,6 +254,11 @@  bool __init xen_hvm_need_lapic(void)
 	return true;
 }
 
+static bool __init msi_ext_dest_id(void)
+{
+       return cpuid_eax(xen_cpuid_base() + 4) & XEN_HVM_CPUID_EXT_DEST_ID;
+}
+
 static __init void xen_hvm_guest_late_init(void)
 {
 #ifdef CONFIG_XEN_PVH
@@ -316,6 +321,7 @@  struct hypervisor_x86 x86_hyper_xen_hvm __initdata = {
 	.init.x2apic_available  = xen_x2apic_para_available,
 	.init.init_mem_mapping	= xen_hvm_init_mem_mapping,
 	.init.guest_late_init	= xen_hvm_guest_late_init,
+	.init.msi_ext_dest_id   = msi_ext_dest_id,
 	.runtime.pin_vcpu       = xen_pin_vcpu,
 	.ignore_nopv            = true,
 };