| Message ID | 20220310195740.151250-1-dinguyen@kernel.org (mailing list archive) |
|---|---|
| State | Queued |
| Headers | show |
| Series | [GIT,PULL,1/2] arm64: dts: socfpga: dts updates for v5.18, part 2 | expand |
On Thu, Mar 10, 2022 at 8:57 PM Dinh Nguyen <dinguyen@kernel.org> wrote: > > The following changes since commit e783362eb54cd99b2cac8b3a9aeac942e6f6ac07: > > Linux 5.17-rc1 (2022-01-23 10:12:53 +0200) > > are available in the Git repository at: > > git@gitolite.kernel.org:pub/scm/linux/kernel/git/dinguyen/linux.git tags/socfpga_dts_update_for_v5.18_part2 I've pulled both manually, but note that these should be public https:// addresses instead of the addresses you for pushing. You can configure a "pushurl" in your .git/config. Arnd
On 3/11/22 04:29, Arnd Bergmann wrote: > On Thu, Mar 10, 2022 at 8:57 PM Dinh Nguyen <dinguyen@kernel.org> wrote: >> >> The following changes since commit e783362eb54cd99b2cac8b3a9aeac942e6f6ac07: >> >> Linux 5.17-rc1 (2022-01-23 10:12:53 +0200) >> >> are available in the Git repository at: >> >> git@gitolite.kernel.org:pub/scm/linux/kernel/git/dinguyen/linux.git tags/socfpga_dts_update_for_v5.18_part2 > > I've pulled both manually, but note that these should be public > https:// addresses > instead of the addresses you for pushing. You can configure a "pushurl" in your > .git/config. > > Arnd Sorry for that mistake! Thanks for the pull! Dinh
The following changes since commit e783362eb54cd99b2cac8b3a9aeac942e6f6ac07: Linux 5.17-rc1 (2022-01-23 10:12:53 +0200) are available in the Git repository at: git@gitolite.kernel.org:pub/scm/linux/kernel/git/dinguyen/linux.git tags/socfpga_dts_update_for_v5.18_part2 for you to fetch changes up to ef82c9be844f6b249a69d8fa190d4d686121d55c: arm64: dts: n5x: add sdr edac support (2022-03-01 09:43:15 -0600) ---------------------------------------------------------------- SoCFPGA dts updates for v5.18, part 2 - More dt-bindings cleanup, this time, USB DWC2 properties - Add SDR EDAC dts entry for the N5X platform ---------------------------------------------------------------- Dinh Nguyen (3): ARM: dts: socfpga: arria10: align regulator node with dtschema ARM: dts: socfpga: cyclone5: align regulator node with dtschema arm64: dts: n5x: add sdr edac support Krzysztof Kozlowski (24): dt-bindings: altera: document existing Cyclone 5 board compatibles dt-bindings: altera: document Arria 5 based board compatibles dt-bindings: altera: document Arria 10 based board compatibles dt-bindings: altera: document VT compatibles dt-bindings: altera: document Stratix 10 based board compatibles dt-bindings: intel: document Agilex based board compatibles dt-bindings: clock: intel,stratix10: convert to dtschema ARM: dts: arria5: add board compatible for SoCFPGA DK ARM: dts: arria10: add board compatible for Mercury AA1 ARM: dts: arria10: add board compatible for SoCFPGA DK arm64: dts: stratix10: add board compatible for SoCFPGA DK arm64: dts: stratix10: move ARM timer out of SoC node arm64: dts: stratix10: align mmc node names with dtschema arm64: dts: stratix10: align regulator node names with dtschema arm64: dts: agilex: add board compatible for SoCFPGA DK arm64: dts: agilex: add board compatible for N5X DK arm64: dts: agilex: align mmc node names with dtschema arm64: dts: intel: socfpga_agilex_socdk: align LED node names with dtschema arm64: dts: stratix10: align pl330 node name with dtschema arm64: dts: agilex: align pl330 node name with dtschema dt-bindings: usb: dwc2: fix compatible of Intel Agilex dt-bindings: usb: dwc2: add iommus dt-bindings: usb: dwc2: add disable-over-current arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node Documentation/devicetree/bindings/arm/altera.yaml | 46 +++++++++++++++++++--- .../devicetree/bindings/arm/intel,socfpga.yaml | 26 ++++++++++++ .../devicetree/bindings/clock/intc_stratix10.txt | 20 ---------- .../devicetree/bindings/clock/intel,stratix10.yaml | 35 ++++++++++++++++ Documentation/devicetree/bindings/usb/dwc2.yaml | 8 ++++ arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts | 2 +- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 2 +- arch/arm/boot/dts/socfpga_arria5_socdk.dts | 4 +- arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts | 2 +- .../arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts | 2 +- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 2 +- arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 2 +- arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 2 +- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 24 +++++------ .../boot/dts/altera/socfpga_stratix10_socdk.dts | 3 +- .../dts/altera/socfpga_stratix10_socdk_nand.dts | 3 +- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 5 ++- arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 7 ++-- .../boot/dts/intel/socfpga_agilex_socdk_nand.dts | 1 + arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 11 ++++++ 20 files changed, 154 insertions(+), 53 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/intel,socfpga.yaml delete mode 100644 Documentation/devicetree/bindings/clock/intc_stratix10.txt create mode 100644 Documentation/devicetree/bindings/clock/intel,stratix10.yaml