diff mbox series

[8/8] drm/i915/dmc: split out dmc registers to a separate file

Message ID 6b3a6acadc33afb7171ca87e958341d1ac244f5b.1647542120.git.jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/dmc: cleanups | expand

Commit Message

Jani Nikula March 17, 2022, 6:36 p.m. UTC 
Clean up the massive i915_reg.h a bit with this isolated set of
registers.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c      |  1 +
 drivers/gpu/drm/i915/display/intel_dmc_regs.h | 31 +++++++++++++++++++
 drivers/gpu/drm/i915/gvt/handlers.c           |  1 +
 drivers/gpu/drm/i915/i915_reg.h               | 21 -------------
 4 files changed, 33 insertions(+), 21 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_regs.h

Comments

Lucas De Marchi March 17, 2022, 7:59 p.m. UTC | #1 
On Thu, Mar 17, 2022 at 08:36:20PM +0200, Jani Nikula wrote:
>Clean up the massive i915_reg.h a bit with this isolated set of
>registers.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_dmc.c      |  1 +
> drivers/gpu/drm/i915/display/intel_dmc_regs.h | 31 +++++++++++++++++++
> drivers/gpu/drm/i915/gvt/handlers.c           |  1 +
> drivers/gpu/drm/i915/i915_reg.h               | 21 -------------
> 4 files changed, 33 insertions(+), 21 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_regs.h
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index 7b7c757ce0ee..4d292a016ca0 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -28,6 +28,7 @@
> #include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_dmc.h"
>+#include "intel_dmc_regs.h"
>
> /**
>  * DOC: DMC Firmware Support
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
>new file mode 100644
>index 000000000000..e436fe93a2da
>--- /dev/null
>+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
>@@ -0,0 +1,31 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2022 Intel Corporation
>+ */
>+
>+#ifndef __INTEL_DMC_REGS_H__
>+#define __INTEL_DMC_REGS_H__
>+
>+#include "i915_reg_defs.h"
>+
>+#define DMC_PROGRAM(addr, i)	_MMIO((addr) + (i) * 4)
>+#define DMC_SSP_BASE_ADDR_GEN9	0x00002FC0
>+#define DMC_HTP_ADDR_SKL	0x00500034
>+#define DMC_SSP_BASE		_MMIO(0x8F074)
>+#define DMC_HTP_SKL		_MMIO(0x8F004)
>+#define DMC_LAST_WRITE		_MMIO(0x8F034)
>+#define DMC_LAST_WRITE_VALUE	0xc003b400
>+/* MMIO address range for DMC program (0x80000 - 0x82FFF) */

this comment seems outdated. Or at least unneeded

Anyway:

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>+#define DMC_MMIO_START_RANGE	0x80000
>+#define DMC_MMIO_END_RANGE	0x8FFFF
>+#define SKL_DMC_DC3_DC5_COUNT	_MMIO(0x80030)
>+#define SKL_DMC_DC5_DC6_COUNT	_MMIO(0x8002C)
>+#define BXT_DMC_DC3_DC5_COUNT	_MMIO(0x80038)
>+#define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
>+#define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
>+#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
>+
>+#define TGL_DMC_DEBUG3		_MMIO(0x101090)
>+#define DG1_DMC_DEBUG3		_MMIO(0x13415c)
>+
>+#endif /* __INTEL_DMC_REGS_H__ */
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 7b7c757ce0ee..4d292a016ca0 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -28,6 +28,7 @@ 
 #include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_dmc.h"
+#include "intel_dmc_regs.h"
 
 /**
  * DOC: DMC Firmware Support
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
new file mode 100644
index 000000000000..e436fe93a2da
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -0,0 +1,31 @@ 
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_DMC_REGS_H__
+#define __INTEL_DMC_REGS_H__
+
+#include "i915_reg_defs.h"
+
+#define DMC_PROGRAM(addr, i)	_MMIO((addr) + (i) * 4)
+#define DMC_SSP_BASE_ADDR_GEN9	0x00002FC0
+#define DMC_HTP_ADDR_SKL	0x00500034
+#define DMC_SSP_BASE		_MMIO(0x8F074)
+#define DMC_HTP_SKL		_MMIO(0x8F004)
+#define DMC_LAST_WRITE		_MMIO(0x8F034)
+#define DMC_LAST_WRITE_VALUE	0xc003b400
+/* MMIO address range for DMC program (0x80000 - 0x82FFF) */
+#define DMC_MMIO_START_RANGE	0x80000
+#define DMC_MMIO_END_RANGE	0x8FFFF
+#define SKL_DMC_DC3_DC5_COUNT	_MMIO(0x80030)
+#define SKL_DMC_DC5_DC6_COUNT	_MMIO(0x8002C)
+#define BXT_DMC_DC3_DC5_COUNT	_MMIO(0x80038)
+#define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
+#define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
+#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
+
+#define TGL_DMC_DEBUG3		_MMIO(0x101090)
+#define DG1_DMC_DEBUG3		_MMIO(0x13415c)
+
+#endif /* __INTEL_DMC_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 0ee3ecc83234..57b0f4977760 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -42,6 +42,7 @@ 
 #include "i915_pvinfo.h"
 #include "intel_mchbar_regs.h"
 #include "display/intel_display_types.h"
+#include "display/intel_dmc_regs.h"
 #include "display/intel_fbc.h"
 #include "display/vlv_dsi_pll_regs.h"
 #include "gt/intel_gt_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4a10b00a585b..25e981406170 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5493,27 +5493,6 @@ 
 #define  GAMMA_MODE_MODE_SPLIT	(3 << 0) /* ivb-bdw */
 #define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED	(3 << 0) /* icl + */
 
-/* DMC */
-#define DMC_PROGRAM(addr, i)	_MMIO((addr) + (i) * 4)
-#define DMC_SSP_BASE_ADDR_GEN9	0x00002FC0
-#define DMC_HTP_ADDR_SKL	0x00500034
-#define DMC_SSP_BASE		_MMIO(0x8F074)
-#define DMC_HTP_SKL		_MMIO(0x8F004)
-#define DMC_LAST_WRITE		_MMIO(0x8F034)
-#define DMC_LAST_WRITE_VALUE	0xc003b400
-/* MMIO address range for DMC program (0x80000 - 0x82FFF) */
-#define DMC_MMIO_START_RANGE	0x80000
-#define DMC_MMIO_END_RANGE	0x8FFFF
-#define SKL_DMC_DC3_DC5_COUNT	_MMIO(0x80030)
-#define SKL_DMC_DC5_DC6_COUNT	_MMIO(0x8002C)
-#define BXT_DMC_DC3_DC5_COUNT	_MMIO(0x80038)
-#define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
-#define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
-#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
-
-#define TGL_DMC_DEBUG3		_MMIO(0x101090)
-#define DG1_DMC_DEBUG3		_MMIO(0x13415c)
-
 /* Display Internal Timeout Register */
 #define RM_TIMEOUT		_MMIO(0x42060)
 #define  MMIO_TIMEOUT_US(us)	((us) << 0)