| Message ID | 20220323090025.546808-1-apatel@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RISC-V: Enable perf events by default | expand |
On Wed, Mar 23, 2022 at 2:00 AM Anup Patel <apatel@ventanamicro.com> wrote: > > Let us enable perf events by default in RV32 and RV64 defconfigs > so that we can use RISC-V PMU drivers on various RISC-V platforms. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > arch/riscv/configs/defconfig | 1 + > arch/riscv/configs/rv32_defconfig | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > index f120fcc43d0a..57aaedc7cf74 100644 > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y > CONFIG_BLK_DEV_INITRD=y > CONFIG_EXPERT=y > # CONFIG_SYSFS_SYSCALL is not set > +CONFIG_PERF_EVENTS=y > CONFIG_SOC_MICROCHIP_POLARFIRE=y > CONFIG_SOC_SIFIVE=y > CONFIG_SOC_VIRT=y > diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig > index 8b56a7f1eb06..21d422e740d5 100644 > --- a/arch/riscv/configs/rv32_defconfig > +++ b/arch/riscv/configs/rv32_defconfig > @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y > CONFIG_BLK_DEV_INITRD=y > CONFIG_EXPERT=y > # CONFIG_SYSFS_SYSCALL is not set > +CONFIG_PERF_EVENTS=y > CONFIG_SOC_SIFIVE=y > CONFIG_SOC_VIRT=y > CONFIG_ARCH_RV32I=y > -- > 2.25.1 > I think it is better to enable perf events by adding CONFIG_PROFILING to the defconfig similar to other ISAs.
On Wed, Mar 23, 2022 at 10:04 PM Atish Patra <atishp@atishpatra.org> wrote: > > On Wed, Mar 23, 2022 at 2:00 AM Anup Patel <apatel@ventanamicro.com> wrote: > > > > Let us enable perf events by default in RV32 and RV64 defconfigs > > so that we can use RISC-V PMU drivers on various RISC-V platforms. > > > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > --- > > arch/riscv/configs/defconfig | 1 + > > arch/riscv/configs/rv32_defconfig | 1 + > > 2 files changed, 2 insertions(+) > > > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > > index f120fcc43d0a..57aaedc7cf74 100644 > > --- a/arch/riscv/configs/defconfig > > +++ b/arch/riscv/configs/defconfig > > @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y > > CONFIG_BLK_DEV_INITRD=y > > CONFIG_EXPERT=y > > # CONFIG_SYSFS_SYSCALL is not set > > +CONFIG_PERF_EVENTS=y > > CONFIG_SOC_MICROCHIP_POLARFIRE=y > > CONFIG_SOC_SIFIVE=y > > CONFIG_SOC_VIRT=y > > diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig > > index 8b56a7f1eb06..21d422e740d5 100644 > > --- a/arch/riscv/configs/rv32_defconfig > > +++ b/arch/riscv/configs/rv32_defconfig > > @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y > > CONFIG_BLK_DEV_INITRD=y > > CONFIG_EXPERT=y > > # CONFIG_SYSFS_SYSCALL is not set > > +CONFIG_PERF_EVENTS=y > > CONFIG_SOC_SIFIVE=y > > CONFIG_SOC_VIRT=y > > CONFIG_ARCH_RV32I=y > > -- > > 2.25.1 > > > > I think it is better to enable perf events by adding CONFIG_PROFILING > to the defconfig similar to other ISAs. Sure, I will update this patch like you suggested. Regards, Anup > > -- > Regards, > Atish
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index f120fcc43d0a..57aaedc7cf74 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y # CONFIG_SYSFS_SYSCALL is not set +CONFIG_PERF_EVENTS=y CONFIG_SOC_MICROCHIP_POLARFIRE=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig index 8b56a7f1eb06..21d422e740d5 100644 --- a/arch/riscv/configs/rv32_defconfig +++ b/arch/riscv/configs/rv32_defconfig @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y # CONFIG_SYSFS_SYSCALL is not set +CONFIG_PERF_EVENTS=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y CONFIG_ARCH_RV32I=y
Let us enable perf events by default in RV32 and RV64 defconfigs so that we can use RISC-V PMU drivers on various RISC-V platforms. Signed-off-by: Anup Patel <apatel@ventanamicro.com> --- arch/riscv/configs/defconfig | 1 + arch/riscv/configs/rv32_defconfig | 1 + 2 files changed, 2 insertions(+)