| Message ID | 20220324000710.575331-10-heiko@sntech.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: support for Svpbmt and D1 memory types | expand |
On Thu, Mar 24, 2022 at 01:07:05AM +0100, Heiko Stuebner wrote: > On rv32 the PFN part of PTEs is defined to use bits [xlen-1:10] > while on rv64 it is defined to use bits [53:10], leaving [63:54] > as reserved. > > With upcoming optional extensions like svpbmt these previously > reserved bits will get used so simply right-shifting the PTE > to get the PFN won't be enough. > > So introduce a _PAGE_PFN_MASK constant to mask the correct bits > for both rv32 and rv64 before shifting. > > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > --- > arch/riscv/include/asm/pgtable-32.h | 8 ++++++++ > arch/riscv/include/asm/pgtable-64.h | 14 +++++++++++--- > arch/riscv/include/asm/pgtable-bits.h | 6 ------ > arch/riscv/include/asm/pgtable.h | 6 +++--- > 4 files changed, 22 insertions(+), 12 deletions(-) > > diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h > index 5b2e79e5bfa5..e266a4fe7f43 100644 > --- a/arch/riscv/include/asm/pgtable-32.h > +++ b/arch/riscv/include/asm/pgtable-32.h > @@ -7,6 +7,7 @@ > #define _ASM_RISCV_PGTABLE_32_H > > #include <asm-generic/pgtable-nopmd.h> > +#include <linux/bits.h> > #include <linux/const.h> > > /* Size of region mapped by a page global directory */ > @@ -16,4 +17,11 @@ > > #define MAX_POSSIBLE_PHYSMEM_BITS 34 > > +/* > + * rv32 PTE format: > + * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 > + * PFN reserved for SW D A G U X W R V > + */ > +#define _PAGE_PFN_MASK GENMASK(31, 10) I have to say I really hate this obsfucating GENMASK macro, but it does have a few other uses in the riscv code. > +/* > + * rv64 PTE format: > + * | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 > + * N MT RSV PFN reserved for SW D A G U X W R V > + */ > > +#define _PAGE_PFN_MASK GENMASK(53, 10) > + > static inline int pud_present(pud_t pud) > { > return (pud_val(pud) & _PAGE_PRESENT); > @@ -91,12 +99,12 @@ static inline unsigned long _pud_pfn(pud_t pud) > > static inline pmd_t *pud_pgtable(pud_t pud) > { > - return (pmd_t *)pfn_to_virt(pud_val(pud) >> _PAGE_PFN_SHIFT); > + return (pmd_t *)pfn_to_virt((pud_val(pud) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT); Lots of overly long lins making this pretty unreadable. But in general the (pfn & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT logic really should have a helper anyway.
diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h index 5b2e79e5bfa5..e266a4fe7f43 100644 --- a/arch/riscv/include/asm/pgtable-32.h +++ b/arch/riscv/include/asm/pgtable-32.h @@ -7,6 +7,7 @@ #define _ASM_RISCV_PGTABLE_32_H #include <asm-generic/pgtable-nopmd.h> +#include <linux/bits.h> #include <linux/const.h> /* Size of region mapped by a page global directory */ @@ -16,4 +17,11 @@ #define MAX_POSSIBLE_PHYSMEM_BITS 34 +/* + * rv32 PTE format: + * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 + * PFN reserved for SW D A G U X W R V + */ +#define _PAGE_PFN_MASK GENMASK(31, 10) + #endif /* _ASM_RISCV_PGTABLE_32_H */ diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h index bbbdd66e5e2f..9412c6157c88 100644 --- a/arch/riscv/include/asm/pgtable-64.h +++ b/arch/riscv/include/asm/pgtable-64.h @@ -6,6 +6,7 @@ #ifndef _ASM_RISCV_PGTABLE_64_H #define _ASM_RISCV_PGTABLE_64_H +#include <linux/bits.h> #include <linux/const.h> extern bool pgtable_l4_enabled; @@ -48,6 +49,13 @@ typedef struct { #define PTRS_PER_PMD (PAGE_SIZE / sizeof(pmd_t)) +/* + * rv64 PTE format: + * | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 + * N MT RSV PFN reserved for SW D A G U X W R V + */ +#define _PAGE_PFN_MASK GENMASK(53, 10) + static inline int pud_present(pud_t pud) { return (pud_val(pud) & _PAGE_PRESENT); @@ -91,12 +99,12 @@ static inline unsigned long _pud_pfn(pud_t pud) static inline pmd_t *pud_pgtable(pud_t pud) { - return (pmd_t *)pfn_to_virt(pud_val(pud) >> _PAGE_PFN_SHIFT); + return (pmd_t *)pfn_to_virt((pud_val(pud) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT); } static inline struct page *pud_page(pud_t pud) { - return pfn_to_page(pud_val(pud) >> _PAGE_PFN_SHIFT); + return pfn_to_page((pud_val(pud) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT); } #define mm_pud_folded mm_pud_folded @@ -117,7 +125,7 @@ static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot) static inline unsigned long _pmd_pfn(pmd_t pmd) { - return pmd_val(pmd) >> _PAGE_PFN_SHIFT; + return (pmd_val(pmd) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT; } #define mk_pmd(page, prot) pfn_pmd(page_to_pfn(page), prot) diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h index a6b0c89824c2..e571fa954afc 100644 --- a/arch/riscv/include/asm/pgtable-bits.h +++ b/arch/riscv/include/asm/pgtable-bits.h @@ -6,12 +6,6 @@ #ifndef _ASM_RISCV_PGTABLE_BITS_H #define _ASM_RISCV_PGTABLE_BITS_H -/* - * PTE format: - * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 - * PFN reserved for SW D A G U X W R V - */ - #define _PAGE_ACCESSED_OFFSET 6 #define _PAGE_PRESENT (1 << 0) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index e3549e50de95..6d31489818cd 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -259,12 +259,12 @@ static inline unsigned long _pgd_pfn(pgd_t pgd) static inline struct page *pmd_page(pmd_t pmd) { - return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT); + return pfn_to_page((pmd_val(pmd) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT); } static inline unsigned long pmd_page_vaddr(pmd_t pmd) { - return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT); + return (unsigned long)pfn_to_virt((pmd_val(pmd) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT); } static inline pte_t pmd_pte(pmd_t pmd) @@ -280,7 +280,7 @@ static inline pte_t pud_pte(pud_t pud) /* Yields the page frame number (PFN) of a page table entry */ static inline unsigned long pte_pfn(pte_t pte) { - return (pte_val(pte) >> _PAGE_PFN_SHIFT); + return ((pte_val(pte) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT); } #define pte_page(x) pfn_to_page(pte_pfn(x))
On rv32 the PFN part of PTEs is defined to use bits [xlen-1:10] while on rv64 it is defined to use bits [53:10], leaving [63:54] as reserved. With upcoming optional extensions like svpbmt these previously reserved bits will get used so simply right-shifting the PTE to get the PFN won't be enough. So introduce a _PAGE_PFN_MASK constant to mask the correct bits for both rv32 and rv64 before shifting. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- arch/riscv/include/asm/pgtable-32.h | 8 ++++++++ arch/riscv/include/asm/pgtable-64.h | 14 +++++++++++--- arch/riscv/include/asm/pgtable-bits.h | 6 ------ arch/riscv/include/asm/pgtable.h | 6 +++--- 4 files changed, 22 insertions(+), 12 deletions(-)