[v4,04/12] ath11k: Add register access logic for WCN6750

Message ID	20220406094107.17878-5-quic_mpubbise@quicinc.com (mailing list archive)
State	Changes Requested
Delegated to:	Kalle Valo
Headers	show Return-Path: <linux-wireless-owner@kernel.org> From: Manikanta Pubbisetty <quic_mpubbise@quicinc.com> To: <ath11k@lists.infradead.org> CC: <linux-wireless@vger.kernel.org>, <devicetree@vger.kernel.org>, <robh@kernel.org>, <mka@chromium.org>, Manikanta Pubbisetty <quic_mpubbise@quicinc.com> Subject: [PATCH v4 04/12] ath11k: Add register access logic for WCN6750 Date: Wed, 6 Apr 2022 15:10:58 +0530 Message-ID: <20220406094107.17878-5-quic_mpubbise@quicinc.com> In-Reply-To: <20220406094107.17878-1-quic_mpubbise@quicinc.com> References: <20220406094107.17878-1-quic_mpubbise@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk
Series	add support for WCN6750 \| expand [v4,00/12] add support for WCN6750 [v4,01/12] dt: bindings: net: add bindings of WCN6750 for ath11k [v4,02/12] ath11k: Add HW params for WCN6750 [v4,03/12] ath11k: Add bus params for WCN6750 [v4,04/12] ath11k: Add register access logic for WCN6750 [v4,05/12] ath11k: Fetch device information via QMI for WCN6750 [v4,06/12] ath11k: Add QMI changes for WCN6750 [v4,07/12] ath11k: HAL changes to support WCN6750 [v4,08/12] ath11k: Datapath changes to support WCN6750 [v4,09/12] ath11k: Do not put HW in DBS mode for WCN6750 [v4,10/12] ath11k: WMI changes to support WCN6750 [v4,11/12] ath11k: Update WBM idle ring HP after FW mode on [v4,12/12] ath11k: Add support for WCN6750 device

Message ID

20220406094107.17878-5-quic_mpubbise@quicinc.com (mailing list archive)

State

Changes Requested

Delegated to:

Kalle Valo

Headers

From: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
To: <ath11k@lists.infradead.org>
CC: <linux-wireless@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <robh@kernel.org>, <mka@chromium.org>,
        Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
Subject: [PATCH v4 04/12] ath11k: Add register access logic for WCN6750
Date: Wed, 6 Apr 2022 15:10:58 +0530
Message-ID: <20220406094107.17878-5-quic_mpubbise@quicinc.com>
In-Reply-To: <20220406094107.17878-1-quic_mpubbise@quicinc.com>
References: <20220406094107.17878-1-quic_mpubbise@quicinc.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
Precedence: bulk

Series

add support for WCN6750 | expand

Commit Message

Manikanta Pubbisetty April 6, 2022, 9:40 a.m. UTC

WCN6750 uses static window mapping to access the HW registers.
Unlike QCN9074 which uses 2nd window for CE and 3rd window
for UMAC register accesses, WCN6750 uses 1st window for UMAC
and 2nd window for CE registers.

Code is refactored so that WCN6750 can use the existing
ath11k_pci_read/write() APIs for accessing the registers.

Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1

Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
---
 drivers/net/wireless/ath/ath11k/ahb.c  |  3 ++
 drivers/net/wireless/ath/ath11k/core.h |  2 +
 drivers/net/wireless/ath/ath11k/pci.c  |  4 ++
 drivers/net/wireless/ath/ath11k/pcic.c | 53 +++++++++-----------------
 4 files changed, 28 insertions(+), 34 deletions(-)

Comments

Kalle Valo April 27, 2022, 5:45 a.m. UTC | #1

Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:

> WCN6750 uses static window mapping to access the HW registers.
> Unlike QCN9074 which uses 2nd window for CE and 3rd window
> for UMAC register accesses, WCN6750 uses 1st window for UMAC
> and 2nd window for CE registers.
>
> Code is refactored so that WCN6750 can use the existing
> ath11k_pci_read/write() APIs for accessing the registers.
>
> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>
> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
> ---
>  drivers/net/wireless/ath/ath11k/ahb.c  |  3 ++
>  drivers/net/wireless/ath/ath11k/core.h |  2 +
>  drivers/net/wireless/ath/ath11k/pci.c  |  4 ++
>  drivers/net/wireless/ath/ath11k/pcic.c | 53 +++++++++-----------------
>  4 files changed, 28 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/net/wireless/ath/ath11k/ahb.c b/drivers/net/wireless/ath/ath11k/ahb.c
> index d73643e3e8dd..d27fc7276977 100644
> --- a/drivers/net/wireless/ath/ath11k/ahb.c
> +++ b/drivers/net/wireless/ath/ath11k/ahb.c
> @@ -42,6 +42,9 @@ const struct ath11k_bus_params ath11k_ahb_hybrid_bus_params = {
>  	.fixed_bdf_addr = false,
>  	.fixed_mem_region = false,
>  	.hybrid_bus_type = true,
> +	.static_window_map = true,
> +	.dp_window_idx = 1,
> +	.ce_window_idx = 2,
>  };

Even if the values are zero, please initialise the new fields in every
bus_params structure:

ahb.c:31:static const struct ath11k_bus_params ath11k_ahb_bus_params = {
pci.c:118:static const struct ath11k_bus_params ath11k_pci_bus_params = {

> --- a/drivers/net/wireless/ath/ath11k/pci.c
> +++ b/drivers/net/wireless/ath/ath11k/pci.c
> @@ -771,6 +771,10 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
>  		ab->bus_params.static_window_map = true;
>  		ab->pci.ops = &ath11k_pci_ops_qcn9074;
>  		ab->hw_rev = ATH11K_HW_QCN9074_HW10;
> +
> +		/* For QCN9074, CE: 2nd window, UMAC: 3rd window */
> +		ab->bus_params.ce_window_idx = 2;
> +		ab->bus_params.dp_window_idx = 3;

Bus params are supposed to be const so that you cannot change them. If
there are device specific attributes they should be in hw_params.

I see now that both hw_params and bus_params are not const in struct
ath11k_base and that's why you were able to change them:

	struct ath11k_hw_params hw_params;
	struct ath11k_bus_params bus_params;

I'll send a separate patch to fix that.

Manikanta Pubbisetty April 27, 2022, 5:53 a.m. UTC | #2

On 4/27/2022 11:15 AM, Kalle Valo wrote:
> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
> 
>> WCN6750 uses static window mapping to access the HW registers.
>> Unlike QCN9074 which uses 2nd window for CE and 3rd window
>> for UMAC register accesses, WCN6750 uses 1st window for UMAC
>> and 2nd window for CE registers.
>>
>> Code is refactored so that WCN6750 can use the existing
>> ath11k_pci_read/write() APIs for accessing the registers.
>>
>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>
>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>> ---
>>   drivers/net/wireless/ath/ath11k/ahb.c  |  3 ++
>>   drivers/net/wireless/ath/ath11k/core.h |  2 +
>>   drivers/net/wireless/ath/ath11k/pci.c  |  4 ++
>>   drivers/net/wireless/ath/ath11k/pcic.c | 53 +++++++++-----------------
>>   4 files changed, 28 insertions(+), 34 deletions(-)
>>
>> diff --git a/drivers/net/wireless/ath/ath11k/ahb.c b/drivers/net/wireless/ath/ath11k/ahb.c
>> index d73643e3e8dd..d27fc7276977 100644
>> --- a/drivers/net/wireless/ath/ath11k/ahb.c
>> +++ b/drivers/net/wireless/ath/ath11k/ahb.c
>> @@ -42,6 +42,9 @@ const struct ath11k_bus_params ath11k_ahb_hybrid_bus_params = {
>>   	.fixed_bdf_addr = false,
>>   	.fixed_mem_region = false,
>>   	.hybrid_bus_type = true,
>> +	.static_window_map = true,
>> +	.dp_window_idx = 1,
>> +	.ce_window_idx = 2,
>>   };
> 
> Even if the values are zero, please initialise the new fields in every
> bus_params structure:
> 
> ahb.c:31:static const struct ath11k_bus_params ath11k_ahb_bus_params = {
> pci.c:118:static const struct ath11k_bus_params ath11k_pci_bus_params = {
>

Makes sense, should I send another series addressing these?

Kalle Valo April 29, 2022, 8:57 a.m. UTC | #3

Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:

> On 4/27/2022 11:15 AM, Kalle Valo wrote:
>> Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
>>
>>> WCN6750 uses static window mapping to access the HW registers.
>>> Unlike QCN9074 which uses 2nd window for CE and 3rd window
>>> for UMAC register accesses, WCN6750 uses 1st window for UMAC
>>> and 2nd window for CE registers.
>>>
>>> Code is refactored so that WCN6750 can use the existing
>>> ath11k_pci_read/write() APIs for accessing the registers.
>>>
>>> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
>>> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>>> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
>>> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>>>
>>> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>>> ---
>>>   drivers/net/wireless/ath/ath11k/ahb.c  |  3 ++
>>>   drivers/net/wireless/ath/ath11k/core.h |  2 +
>>>   drivers/net/wireless/ath/ath11k/pci.c  |  4 ++
>>>   drivers/net/wireless/ath/ath11k/pcic.c | 53 +++++++++-----------------
>>>   4 files changed, 28 insertions(+), 34 deletions(-)
>>>
>>> diff --git a/drivers/net/wireless/ath/ath11k/ahb.c b/drivers/net/wireless/ath/ath11k/ahb.c
>>> index d73643e3e8dd..d27fc7276977 100644
>>> --- a/drivers/net/wireless/ath/ath11k/ahb.c
>>> +++ b/drivers/net/wireless/ath/ath11k/ahb.c
>>> @@ -42,6 +42,9 @@ const struct ath11k_bus_params ath11k_ahb_hybrid_bus_params = {
>>>   	.fixed_bdf_addr = false,
>>>   	.fixed_mem_region = false,
>>>   	.hybrid_bus_type = true,
>>> +	.static_window_map = true,
>>> +	.dp_window_idx = 1,
>>> +	.ce_window_idx = 2,
>>>   };
>>
>> Even if the values are zero, please initialise the new fields in every
>> bus_params structure:
>>
>> ahb.c:31:static const struct ath11k_bus_params ath11k_ahb_bus_params = {
>> pci.c:118:static const struct ath11k_bus_params ath11k_pci_bus_params = {
>>
>
> Makes sense, should I send another series addressing these?

Please fix that already in this patchset.

diff --git a/drivers/net/wireless/ath/ath11k/ahb.c b/drivers/net/wireless/ath/ath11k/ahb.c
index d73643e3e8dd..d27fc7276977 100644
--- a/drivers/net/wireless/ath/ath11k/ahb.c
+++ b/drivers/net/wireless/ath/ath11k/ahb.c
@@ -42,6 +42,9 @@  const struct ath11k_bus_params ath11k_ahb_hybrid_bus_params = {
 	.fixed_bdf_addr = false,
 	.fixed_mem_region = false,
 	.hybrid_bus_type = true,
+	.static_window_map = true,
+	.dp_window_idx = 1,
+	.ce_window_idx = 2,
 };
 
 #define ATH11K_IRQ_CE0_OFFSET 4
diff --git a/drivers/net/wireless/ath/ath11k/core.h b/drivers/net/wireless/ath/ath11k/core.h
index b0bb01cc9d04..d3bfaafcd571 100644
--- a/drivers/net/wireless/ath/ath11k/core.h
+++ b/drivers/net/wireless/ath/ath11k/core.h
@@ -730,6 +730,8 @@  struct ath11k_bus_params {
 	bool fixed_mem_region;
 	bool static_window_map;
 	bool hybrid_bus_type;
+	u8 dp_window_idx;
+	u8 ce_window_idx;
 };
 
 struct ath11k_pci_ops {
diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c
index 3fd5b416a564..bd314680f24c 100644
--- a/drivers/net/wireless/ath/ath11k/pci.c
+++ b/drivers/net/wireless/ath/ath11k/pci.c
@@ -771,6 +771,10 @@  static int ath11k_pci_probe(struct pci_dev *pdev,
 		ab->bus_params.static_window_map = true;
 		ab->pci.ops = &ath11k_pci_ops_qcn9074;
 		ab->hw_rev = ATH11K_HW_QCN9074_HW10;
+
+		/* For QCN9074, CE: 2nd window, UMAC: 3rd window */
+		ab->bus_params.ce_window_idx = 2;
+		ab->bus_params.dp_window_idx = 3;
 		break;
 	case WCN6855_DEVICE_ID:
 		ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD;
diff --git a/drivers/net/wireless/ath/ath11k/pcic.c b/drivers/net/wireless/ath/ath11k/pcic.c
index 63c678aea29e..6d0b5307d5c7 100644
--- a/drivers/net/wireless/ath/ath11k/pcic.c
+++ b/drivers/net/wireless/ath/ath11k/pcic.c
@@ -134,16 +134,14 @@  EXPORT_SYMBOL(ath11k_pcic_init_msi_config);
 static inline u32 ath11k_pcic_get_window_start(struct ath11k_base *ab,
 					       u32 offset)
 {
-	u32 window_start;
+	u32 window_start = 0;
 
 	/* If offset lies within DP register range, use 3rd window */
 	if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
-		window_start = 3 * ATH11K_PCI_WINDOW_START;
-	/* If offset lies within CE register range, use 2nd window */
-	else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < ATH11K_PCI_WINDOW_RANGE_MASK)
-		window_start = 2 * ATH11K_PCI_WINDOW_START;
-	else
-		window_start = ATH11K_PCI_WINDOW_START;
+		window_start = ab->bus_params.dp_window_idx * ATH11K_PCI_WINDOW_START;
+	else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
+		 ATH11K_PCI_WINDOW_RANGE_MASK)
+		window_start = ab->bus_params.ce_window_idx * ATH11K_PCI_WINDOW_START;
 
 	return window_start;
 }
@@ -162,19 +160,12 @@  void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value)
 
 	if (offset < ATH11K_PCI_WINDOW_START) {
 		iowrite32(value, ab->mem  + offset);
-	} else {
-		if (ab->bus_params.static_window_map)
-			window_start = ath11k_pcic_get_window_start(ab, offset);
-		else
-			window_start = ATH11K_PCI_WINDOW_START;
-
-		if (window_start == ATH11K_PCI_WINDOW_START &&
-		    ab->pci.ops->window_write32) {
-			ab->pci.ops->window_write32(ab, offset, value);
-		} else {
-			iowrite32(value, ab->mem + window_start +
-				  (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
-		}
+	} else if (ab->bus_params.static_window_map) {
+		window_start = ath11k_pcic_get_window_start(ab, offset);
+		iowrite32(value, ab->mem + window_start +
+			  (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
+	} else if (ab->pci.ops->window_write32) {
+		ab->pci.ops->window_write32(ab, offset, value);
 	}
 
 	if (test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
@@ -185,7 +176,8 @@  void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value)
 
 u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset)
 {
-	u32 val, window_start;
+	u32 val = 0;
+	u32 window_start;
 	int ret = 0;
 
 	/* for offset beyond BAR + 4K - 32, may
@@ -197,19 +189,12 @@  u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset)
 
 	if (offset < ATH11K_PCI_WINDOW_START) {
 		val = ioread32(ab->mem + offset);
-	} else {
-		if (ab->bus_params.static_window_map)
-			window_start = ath11k_pcic_get_window_start(ab, offset);
-		else
-			window_start = ATH11K_PCI_WINDOW_START;
-
-		if (window_start == ATH11K_PCI_WINDOW_START &&
-		    ab->pci.ops->window_read32) {
-			val = ab->pci.ops->window_read32(ab, offset);
-		} else {
-			val = ioread32(ab->mem + window_start +
-				       (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
-		}
+	} else if (ab->bus_params.static_window_map) {
+		window_start = ath11k_pcic_get_window_start(ab, offset);
+		val = ioread32(ab->mem + window_start +
+			       (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
+	} else if (ab->pci.ops->window_read32) {
+		val = ab->pci.ops->window_read32(ab, offset);
 	}
 
 	if (test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&

[v4,04/12] ath11k: Add register access logic for WCN6750

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