| Message ID | 20220223090706.4888-15-damien.hedde@greensocs.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Initial support for machine creation via QMP | expand |
On 23/2/22 10:07, Damien Hedde wrote: > The devices are: > + ibex-timer > + ibex-uart > + riscv.aclint.swi > + riscv.aclint.mtimer > + riscv.hart_array > + riscv.sifive.e.prci > + riscv.sifive.plic > + riscv.sifive.uart > + sifive_soc.gpio > + unimplemented-device > > These devices are clean regarding error handling in realize. > > They are all sysbus devices, so setting user-creatable will only > enable cold-plugging them on machine having explicitely allowed them > (only _none_ machine does that). > > Note that this commit include the ricv_array which embeds cpus. There Typo "includes" I guess. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > are some deep internal constraints about them: you cannot create more > cpus than the machine's maxcpus. TCG accelerator's code will for example > assert if a user try to create too many cpus. > > Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> > --- > > I can also split this patch if you think it's better. > But it is mostly a one-line fix per file. > > This patch requires first some cleanups in order to fix error errors > and some more memory leaks that could happend in legit user-related > life cycles: a miss-configuration should not be a fatal error anymore. > https://lore.kernel.org/qemu-devel/20220218164646.132112-1-damien.hedde@greensocs.com > --- > hw/char/ibex_uart.c | 1 + > hw/char/sifive_uart.c | 1 + > hw/gpio/sifive_gpio.c | 1 + > hw/intc/riscv_aclint.c | 2 ++ > hw/intc/sifive_plic.c | 1 + > hw/misc/sifive_e_prci.c | 8 ++++++++ > hw/misc/unimp.c | 1 + > hw/riscv/riscv_hart.c | 1 + > hw/timer/ibex_timer.c | 1 + > 9 files changed, 17 insertions(+)
Tested-by: Jim Shu <jim.shu@sifive.com> On Fri, Mar 4, 2022 at 11:23 PM Philippe Mathieu-Daudé < philippe.mathieu.daude@gmail.com> wrote: > On 23/2/22 10:07, Damien Hedde wrote: > > The devices are: > > + ibex-timer > > + ibex-uart > > + riscv.aclint.swi > > + riscv.aclint.mtimer > > + riscv.hart_array > > + riscv.sifive.e.prci > > + riscv.sifive.plic > > + riscv.sifive.uart > > + sifive_soc.gpio > > + unimplemented-device > > > > These devices are clean regarding error handling in realize. > > > > They are all sysbus devices, so setting user-creatable will only > > enable cold-plugging them on machine having explicitely allowed them > > (only _none_ machine does that). > > > > Note that this commit include the ricv_array which embeds cpus. There > > Typo "includes" I guess. > > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > > > are some deep internal constraints about them: you cannot create more > > cpus than the machine's maxcpus. TCG accelerator's code will for example > > assert if a user try to create too many cpus. > > > > Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> > > --- > > > > I can also split this patch if you think it's better. > > But it is mostly a one-line fix per file. > > > > This patch requires first some cleanups in order to fix error errors > > and some more memory leaks that could happend in legit user-related > > life cycles: a miss-configuration should not be a fatal error anymore. > > > https://lore.kernel.org/qemu-devel/20220218164646.132112-1-damien.hedde@greensocs.com > > --- > > hw/char/ibex_uart.c | 1 + > > hw/char/sifive_uart.c | 1 + > > hw/gpio/sifive_gpio.c | 1 + > > hw/intc/riscv_aclint.c | 2 ++ > > hw/intc/sifive_plic.c | 1 + > > hw/misc/sifive_e_prci.c | 8 ++++++++ > > hw/misc/unimp.c | 1 + > > hw/riscv/riscv_hart.c | 1 + > > hw/timer/ibex_timer.c | 1 + > > 9 files changed, 17 insertions(+) > >
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c index e58181fcf4..0b6d45f2e7 100644 --- a/hw/char/ibex_uart.c +++ b/hw/char/ibex_uart.c @@ -546,6 +546,7 @@ static void ibex_uart_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + dc->user_creatable = true; dc->reset = ibex_uart_reset; dc->realize = ibex_uart_realize; dc->vmsd = &vmstate_ibex_uart; diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c index 1c75f792b3..6e88778c03 100644 --- a/hw/char/sifive_uart.c +++ b/hw/char/sifive_uart.c @@ -243,6 +243,7 @@ static void sifive_uart_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); ResettableClass *rc = RESETTABLE_CLASS(oc); + dc->user_creatable = true; dc->realize = sifive_uart_realize; dc->vmsd = &vmstate_sifive_uart; rc->phases.enter = sifive_uart_reset_enter; diff --git a/hw/gpio/sifive_gpio.c b/hw/gpio/sifive_gpio.c index 78bf29e996..8443befa20 100644 --- a/hw/gpio/sifive_gpio.c +++ b/hw/gpio/sifive_gpio.c @@ -380,6 +380,7 @@ static void sifive_gpio_class_init(ObjectClass *klass, void *data) dc->realize = sifive_gpio_realize; dc->reset = sifive_gpio_reset; dc->desc = "SiFive GPIO"; + dc->user_creatable = true; } static const TypeInfo sifive_gpio_info = { diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index bef2e1988b..fbf63a52b7 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -283,6 +283,7 @@ static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = riscv_aclint_mtimer_realize; device_class_set_props(dc, riscv_aclint_mtimer_properties); + dc->user_creatable = true; } static const TypeInfo riscv_aclint_mtimer_info = { @@ -466,6 +467,7 @@ static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = riscv_aclint_swi_realize; device_class_set_props(dc, riscv_aclint_swi_properties); + dc->user_creatable = true; } static const TypeInfo riscv_aclint_swi_info = { diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 8692ea6725..4e5831b487 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -434,6 +434,7 @@ static void sifive_plic_class_init(ObjectClass *klass, void *data) dc->reset = sifive_plic_reset; device_class_set_props(dc, sifive_plic_properties); + dc->user_creatable = true; dc->realize = sifive_plic_realize; dc->vmsd = &vmstate_sifive_plic; } diff --git a/hw/misc/sifive_e_prci.c b/hw/misc/sifive_e_prci.c index a8702c6a5d..7341823e43 100644 --- a/hw/misc/sifive_e_prci.c +++ b/hw/misc/sifive_e_prci.c @@ -97,11 +97,19 @@ static void sifive_e_prci_init(Object *obj) s->plloutdiv = SIFIVE_E_PRCI_PLLOUTDIV_DIV1; } +static void sifive_e_prci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->user_creatable = true; +} + static const TypeInfo sifive_e_prci_info = { .name = TYPE_SIFIVE_E_PRCI, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(SiFiveEPRCIState), .instance_init = sifive_e_prci_init, + .class_init = sifive_e_prci_class_init, }; static void sifive_e_prci_register_types(void) diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c index 6cfc5727f0..fb2a0b23dd 100644 --- a/hw/misc/unimp.c +++ b/hw/misc/unimp.c @@ -80,6 +80,7 @@ static void unimp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + dc->user_creatable = true; dc->realize = unimp_realize; device_class_set_props(dc, unimp_properties); } diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 4aed6c2a59..85fae44048 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -77,6 +77,7 @@ static void riscv_harts_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + dc->user_creatable = true; device_class_set_props(dc, riscv_harts_props); dc->realize = riscv_harts_realize; } diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c index 8c2ca364da..d1cc337416 100644 --- a/hw/timer/ibex_timer.c +++ b/hw/timer/ibex_timer.c @@ -295,6 +295,7 @@ static void ibex_timer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + dc->user_creatable = true; dc->reset = ibex_timer_reset; dc->vmsd = &vmstate_ibex_timer; dc->realize = ibex_timer_realize;
The devices are: + ibex-timer + ibex-uart + riscv.aclint.swi + riscv.aclint.mtimer + riscv.hart_array + riscv.sifive.e.prci + riscv.sifive.plic + riscv.sifive.uart + sifive_soc.gpio + unimplemented-device These devices are clean regarding error handling in realize. They are all sysbus devices, so setting user-creatable will only enable cold-plugging them on machine having explicitely allowed them (only _none_ machine does that). Note that this commit include the ricv_array which embeds cpus. There are some deep internal constraints about them: you cannot create more cpus than the machine's maxcpus. TCG accelerator's code will for example assert if a user try to create too many cpus. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> --- I can also split this patch if you think it's better. But it is mostly a one-line fix per file. This patch requires first some cleanups in order to fix error errors and some more memory leaks that could happend in legit user-related life cycles: a miss-configuration should not be a fatal error anymore. https://lore.kernel.org/qemu-devel/20220218164646.132112-1-damien.hedde@greensocs.com --- hw/char/ibex_uart.c | 1 + hw/char/sifive_uart.c | 1 + hw/gpio/sifive_gpio.c | 1 + hw/intc/riscv_aclint.c | 2 ++ hw/intc/sifive_plic.c | 1 + hw/misc/sifive_e_prci.c | 8 ++++++++ hw/misc/unimp.c | 1 + hw/riscv/riscv_hart.c | 1 + hw/timer/ibex_timer.c | 1 + 9 files changed, 17 insertions(+)