Message ID | 20220613195658.5607-13-brad@pensando.io (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Support AMD Pensando Elba SoC | expand |
On Mon, Jun 13, 2022 at 9:57 PM Brad Larson <brad@pensando.io> wrote: > > From: Brad Larson <blarson@amd.com> > > The AMD Pensando Elba SoC includes a DW apb_ssi v4 controller > with device specific chip-select control. The Elba SoC > provides four chip-selects where the native DW IP supports > two chip-selects. The Elba DW_SPI instance has two native > CS signals that are always overridden. ... > +/* > + * Elba SoC does not use ssi, pin override is used for cs 0,1 and > + * gpios for cs 2,3 as defined in the device tree. > + * > + * cs: | 1 0 > + * bit: |---3-------2-------1-------0 > + * | cs1 cs1_ovr cs0 cs0_ovr > + */ > +#define ELBA_SPICS_SHIFT(cs) (2 * (cs)) Useless.It takes much more than simply multiplying each time in two macros. Also see below. > +#define ELBA_SPICS_MASK(cs) (0x3 << ELBA_SPICS_SHIFT(cs)) (GENMASK(1, 0) << ((cs) << 1)) Or ((cs) * 2) to show that it takes 2 bits and not two times of CS', > +#define ELBA_SPICS_SET(cs, val) \ > + ((((val) << 1) | 0x1) << ELBA_SPICS_SHIFT(cs)) BIT(0) So the main point is to use GENMASK() and BIT() the rest is up to you.
Hi Andy, On Tue, Jun 14, 2022 at 4:10 AM Andy Shevchenko <andy.shevchenko@gmail.com> wrote: > > On Mon, Jun 13, 2022 at 9:57 PM Brad Larson <brad@pensando.io> wrote: > ... > > > +/* > > + * Elba SoC does not use ssi, pin override is used for cs 0,1 and > > + * gpios for cs 2,3 as defined in the device tree. > > + * > > + * cs: | 1 0 > > + * bit: |---3-------2-------1-------0 > > + * | cs1 cs1_ovr cs0 cs0_ovr > > + */ > > > +#define ELBA_SPICS_SHIFT(cs) (2 * (cs)) > > Useless.It takes much more than simply multiplying each time in two > macros. Also see below. > > > +#define ELBA_SPICS_MASK(cs) (0x3 << ELBA_SPICS_SHIFT(cs)) > > (GENMASK(1, 0) << ((cs) << 1)) > > Or ((cs) * 2) to show that it takes 2 bits and not two times of CS', > > > +#define ELBA_SPICS_SET(cs, val) \ > > + ((((val) << 1) | 0x1) << ELBA_SPICS_SHIFT(cs)) > > BIT(0) > > So the main point is to use GENMASK() and BIT() the rest is up to you. I think you're recommending this approach which I'll change to static void dw_spi_elba_override_cs(struct dw_spi_elba *dwselba, int cs, int enable) { regmap_update_bits(dwselba->syscon, ELBA_SPICS_REG, (GENMASK(1, 0) << ((cs) << 1)), ((enable) << 1 | BIT(0)) << ((cs) << 1)); } Regards, Brad
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 5101c4c6017b..6b7a557759bd 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -53,6 +53,24 @@ struct dw_spi_mscc { void __iomem *spi_mst; /* Not sparx5 */ }; +struct dw_spi_elba { + struct regmap *syscon; +}; + +/* + * Elba SoC does not use ssi, pin override is used for cs 0,1 and + * gpios for cs 2,3 as defined in the device tree. + * + * cs: | 1 0 + * bit: |---3-------2-------1-------0 + * | cs1 cs1_ovr cs0 cs0_ovr + */ +#define ELBA_SPICS_REG 0x2468 +#define ELBA_SPICS_SHIFT(cs) (2 * (cs)) +#define ELBA_SPICS_MASK(cs) (0x3 << ELBA_SPICS_SHIFT(cs)) +#define ELBA_SPICS_SET(cs, val) \ + ((((val) << 1) | 0x1) << ELBA_SPICS_SHIFT(cs)) + /* * The Designware SPI controller (referred to as master in the documentation) * automatically deasserts chip select when the tx fifo is empty. The chip @@ -238,6 +256,53 @@ static int dw_spi_canaan_k210_init(struct platform_device *pdev, return 0; } +static void dw_spi_elba_override_cs(struct dw_spi_elba *dwselba, int cs, int enable) +{ + regmap_update_bits(dwselba->syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs), + ELBA_SPICS_SET(cs, enable)); +} + +static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable) +{ + struct dw_spi *dws = spi_master_get_devdata(spi->master); + struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws); + struct dw_spi_elba *dwselba = dwsmmio->priv; + u8 cs; + + cs = spi->chip_select; + if (cs < 2) + dw_spi_elba_override_cs(dwselba, spi->chip_select, enable); + + /* + * The DW SPI controller needs a native CS bit selected to start + * the serial engine. + */ + spi->chip_select = 0; + dw_spi_set_cs(spi, enable); + spi->chip_select = cs; +} + +static int dw_spi_elba_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + struct dw_spi_elba *dwselba; + struct regmap *regmap; + + regmap = syscon_regmap_lookup_by_compatible("amd,pensando-elba-syscon"); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + dwselba = devm_kzalloc(&pdev->dev, sizeof(*dwselba), GFP_KERNEL); + if (!dwselba) + return -ENOMEM; + dwselba->syscon = regmap; + + dwsmmio->priv = dwselba; + dwsmmio->dws.set_cs = dw_spi_elba_set_cs; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -352,6 +417,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init}, { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init}, + { .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);