[v2,0/2] perf: RISC-V: fix access beyond allocated array

Message ID	20220624135902.520748-1-geomatsi@gmail.com (mailing list archive)
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> From: Sergey Matyukevich <geomatsi@gmail.com> To: linux-riscv@lists.infradead.org Cc: Atish Patra <atishp@atishpatra.org>, Anup Patel <anup@brainfault.org>, Sergey Matyukevich <geomatsi@gmail.com> Subject: [PATCH v2 0/2] perf: RISC-V: fix access beyond allocated array Date: Fri, 24 Jun 2022 16:59:00 +0300 Message-Id: <20220624135902.520748-1-geomatsi@gmail.com> MIME-Version: 1.0 Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	perf: RISC-V: fix access beyond allocated array \| expand [v2,0/2] perf: RISC-V: fix access beyond allocated array [v2,1/2] perf: RISC-V: fix access beyond allocated array [v2,2/2] perf: RISC-V: exclude invalid pmu counters from SBI calls

Message ID

20220624135902.520748-1-geomatsi@gmail.com (mailing list archive)

Headers

From: Sergey Matyukevich <geomatsi@gmail.com>
To: linux-riscv@lists.infradead.org
Cc: Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>,
	Sergey Matyukevich <geomatsi@gmail.com>
Subject: [PATCH v2 0/2] perf: RISC-V: fix access beyond allocated array
Date: Fri, 24 Jun 2022 16:59:00 +0300
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Series

perf: RISC-V: fix access beyond allocated array | expand

Message

Sergey Matyukevich June 24, 2022, 1:59 p.m. UTC

Hi all,

These patches suggest some fixes and cleanups for the handling of pmu
counters. The first patch fixes access beyond the allocated pmu_ctr_list
array. The second patch fixes the counters mask sent to SBI firmware: it
excludes counters that were not fully specified by SBI firmware on init.

Initial attempt to fix access to the highest available has been reworked.
Now it is handled in the OpenSBI, see the following patch:
- https://patchwork.ozlabs.org/project/opensbi/patch/20220624110330.452640-1-geomatsi@gmail.com/

Regards,
Sergey

v1 -> v2:
- drop changes for access to the highest available counter as they are
  now handled on the OpenSBI side
- drop switch to IDR: in fact there is no need to handle non-contiguous
  counter ranges

Sergey Matyukevich (2):
  perf: RISC-V: fix access beyond allocated array
  perf: RISC-V: exclude invalid pmu counters from SBI calls

 drivers/perf/riscv_pmu_legacy.c |  4 ++--
 drivers/perf/riscv_pmu_sbi.c    | 24 ++++++++++++++----------
 include/linux/perf/riscv_pmu.h  |  2 +-
 3 files changed, 17 insertions(+), 13 deletions(-)

Comments

Sergey Matyukevich Aug. 10, 2022, 7:06 a.m. UTC | #1

Hi Atish, Anup

> These patches suggest some fixes and cleanups for the handling of pmu
> counters. The first patch fixes access beyond the allocated pmu_ctr_list
> array. The second patch fixes the counters mask sent to SBI firmware: it
> excludes counters that were not fully specified by SBI firmware on init.
> 
> Initial attempt to fix access to the highest available has been reworked.
> Now it is handled in the OpenSBI, see the following patch:
> - https://patchwork.ozlabs.org/project/opensbi/patch/20220624110330.452640-1-geomatsi@gmail.com/
> 
> Regards,
> Sergey
> 
> v1 -> v2:
> - drop changes for access to the highest available counter as they are
>   now handled on the OpenSBI side
> - drop switch to IDR: in fact there is no need to handle non-contiguous
>   counter ranges
> 
> Sergey Matyukevich (2):
>   perf: RISC-V: fix access beyond allocated array
>   perf: RISC-V: exclude invalid pmu counters from SBI calls
> 
>  drivers/perf/riscv_pmu_legacy.c |  4 ++--
>  drivers/perf/riscv_pmu_sbi.c    | 24 ++++++++++++++----------
>  include/linux/perf/riscv_pmu.h  |  2 +-
>  3 files changed, 17 insertions(+), 13 deletions(-)

Friendly ping.  I have already received RB tag from Atish for the first
patch. Do you have any concerns with the second one ?

Besides, what is the appropriate merge path for RISC-V PMU driver ?
Are they usually merged via risc-v kernel trees ?

Regards,
Sergey