diff mbox series

[09/11] hw/sd/sdhci: Rename ESDHC_* defines to USDHC_*

Message ID 20220915152520.21948-10-shentey@gmail.com (mailing list archive)
State New, archived
Headers show
Series ppc/e500: Add support for two types of flash, cleanup | expand

Commit Message

Bernhard Beschow Sept. 15, 2022, 3:25 p.m. UTC 
The device model's functions start with "usdhc_", so rename the defines
accordingly for consistency.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
 hw/sd/sdhci.c | 68 +++++++++++++++++++++++++--------------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

Comments

Bin Meng Sept. 16, 2022, 10:07 a.m. UTC | #1 
On Thu, Sep 15, 2022 at 11:42 PM Bernhard Beschow <shentey@gmail.com> wrote:
>
> The device model's functions start with "usdhc_", so rename the defines
> accordingly for consistency.
>
> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
> ---
>  hw/sd/sdhci.c | 68 +++++++++++++++++++++++++--------------------------
>  1 file changed, 34 insertions(+), 34 deletions(-)
>
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index 6da5e2c781..7a5996caad 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -1577,24 +1577,24 @@ static const TypeInfo sdhci_bus_info = {
>
>  /* --- qdev i.MX eSDHC --- */
>
> -#define ESDHC_MIX_CTRL                  0x48
> +#define USDHC_MIX_CTRL                  0x48
>
> -#define ESDHC_VENDOR_SPEC               0xc0
> -#define ESDHC_IMX_FRC_SDCLK_ON          (1 << 8)
> +#define USDHC_VENDOR_SPEC               0xc0
> +#define USDHC_IMX_FRC_SDCLK_ON          (1 << 8)
>
> -#define ESDHC_DLL_CTRL                  0x60
> +#define USDHC_DLL_CTRL                  0x60
>
> -#define ESDHC_TUNING_CTRL               0xcc
> -#define ESDHC_TUNE_CTRL_STATUS          0x68
> -#define ESDHC_WTMK_LVL                  0x44
> +#define USDHC_TUNING_CTRL               0xcc
> +#define USDHC_TUNE_CTRL_STATUS          0x68
> +#define USDHC_WTMK_LVL                  0x44
>
>  /* Undocumented register used by guests working around erratum ERR004536 */
> -#define ESDHC_UNDOCUMENTED_REG27        0x6c
> +#define USDHC_UNDOCUMENTED_REG27        0x6c
>
> -#define ESDHC_CTRL_4BITBUS              (0x1 << 1)
> -#define ESDHC_CTRL_8BITBUS              (0x2 << 1)
> +#define USDHC_CTRL_4BITBUS              (0x1 << 1)
> +#define USDHC_CTRL_8BITBUS              (0x2 << 1)
>
> -#define ESDHC_PRNSTS_SDSTB              (1 << 3)
> +#define USDHC_PRNSTS_SDSTB              (1 << 3)
>
>  static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
>  {
> @@ -1615,11 +1615,11 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
>          hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3);
>
>          if (s->hostctl1 & SDHC_CTRL_8BITBUS) {
> -            hostctl1 |= ESDHC_CTRL_8BITBUS;
> +            hostctl1 |= USDHC_CTRL_8BITBUS;
>          }
>
>          if (s->hostctl1 & SDHC_CTRL_4BITBUS) {
> -            hostctl1 |= ESDHC_CTRL_4BITBUS;
> +            hostctl1 |= USDHC_CTRL_4BITBUS;
>          }
>
>          ret  = hostctl1;
> @@ -1630,21 +1630,21 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
>
>      case SDHC_PRNSTS:
>          /* Add SDSTB (SD Clock Stable) bit to PRNSTS */
> -        ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB;
> +        ret = sdhci_read(opaque, offset, size) & ~USDHC_PRNSTS_SDSTB;
>          if (s->clkcon & SDHC_CLOCK_INT_STABLE) {
> -            ret |= ESDHC_PRNSTS_SDSTB;
> +            ret |= USDHC_PRNSTS_SDSTB;
>          }
>          break;
>
> -    case ESDHC_VENDOR_SPEC:
> +    case USDHC_VENDOR_SPEC:
>          ret = s->vendor_spec;
>          break;
> -    case ESDHC_DLL_CTRL:
> -    case ESDHC_TUNE_CTRL_STATUS:
> -    case ESDHC_UNDOCUMENTED_REG27:
> -    case ESDHC_TUNING_CTRL:
> -    case ESDHC_MIX_CTRL:
> -    case ESDHC_WTMK_LVL:
> +    case USDHC_DLL_CTRL:
> +    case USDHC_TUNE_CTRL_STATUS:
> +    case USDHC_UNDOCUMENTED_REG27:
> +    case USDHC_TUNING_CTRL:
> +    case USDHC_MIX_CTRL:
> +    case USDHC_WTMK_LVL:
>          ret = 0;
>          break;
>      }
> @@ -1660,18 +1660,18 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
>      uint32_t value = (uint32_t)val;
>
>      switch (offset) {
> -    case ESDHC_DLL_CTRL:
> -    case ESDHC_TUNE_CTRL_STATUS:
> -    case ESDHC_UNDOCUMENTED_REG27:
> -    case ESDHC_TUNING_CTRL:
> -    case ESDHC_WTMK_LVL:
> +    case USDHC_DLL_CTRL:
> +    case USDHC_TUNE_CTRL_STATUS:
> +    case USDHC_UNDOCUMENTED_REG27:
> +    case USDHC_TUNING_CTRL:
> +    case USDHC_WTMK_LVL:
>          break;
>
> -    case ESDHC_VENDOR_SPEC:
> +    case USDHC_VENDOR_SPEC:
>          s->vendor_spec = value;
>          switch (s->vendor) {
>          case SDHCI_VENDOR_IMX:
> -            if (value & ESDHC_IMX_FRC_SDCLK_ON) {
> +            if (value & USDHC_IMX_FRC_SDCLK_ON) {
>                  s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF;
>              } else {
>                  s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF;
> @@ -1740,12 +1740,12 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
>           * Second, split "Data Transfer Width" from bits 2 and 1 in to
>           * bits 5 and 1
>           */
> -        if (value & ESDHC_CTRL_8BITBUS) {
> +        if (value & USDHC_CTRL_8BITBUS) {
>              hostctl1 |= SDHC_CTRL_8BITBUS;
>          }
>
> -        if (value & ESDHC_CTRL_4BITBUS) {
> -            hostctl1 |= ESDHC_CTRL_4BITBUS;
> +        if (value & USDHC_CTRL_4BITBUS) {
> +            hostctl1 |= USDHC_CTRL_4BITBUS;
>          }
>
>          /*
> @@ -1768,11 +1768,11 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
>          sdhci_write(opaque, offset, value, size);
>          break;
>
> -    case ESDHC_MIX_CTRL:
> +    case USDHC_MIX_CTRL:
>          /*
>           * So, when SD/MMC stack in Linux tries to write to "Transfer
>           * Mode Register", ESDHC i.MX quirk code will translate it

Here I assume ESDHC i.MX means the Linux eSDHC driver for i.MX, so no
need to replace ESDHC with USDHC?

> -         * into a write to ESDHC_MIX_CTRL, so we do the opposite in
> +         * into a write to USDHC_MIX_CTRL, so we do the opposite in
>           * order to get where we started
>           *
>           * Note that Auto CMD23 Enable bit is located in a wrong place
> --

Overall LGTM:
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bernhard Beschow Sept. 16, 2022, 5:11 p.m. UTC | #2 
Am 16. September 2022 10:07:28 UTC schrieb Bin Meng <bmeng.cn@gmail.com>:
>On Thu, Sep 15, 2022 at 11:42 PM Bernhard Beschow <shentey@gmail.com> wrote:
>>
>> The device model's functions start with "usdhc_", so rename the defines
>> accordingly for consistency.
>>
>> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
>> ---
>>  hw/sd/sdhci.c | 68 +++++++++++++++++++++++++--------------------------
>>  1 file changed, 34 insertions(+), 34 deletions(-)
>>
>> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
>> index 6da5e2c781..7a5996caad 100644
>> --- a/hw/sd/sdhci.c
>> +++ b/hw/sd/sdhci.c
>> @@ -1577,24 +1577,24 @@ static const TypeInfo sdhci_bus_info = {
>>
>>  /* --- qdev i.MX eSDHC --- */
>>
>> -#define ESDHC_MIX_CTRL                  0x48
>> +#define USDHC_MIX_CTRL                  0x48
>>
>> -#define ESDHC_VENDOR_SPEC               0xc0
>> -#define ESDHC_IMX_FRC_SDCLK_ON          (1 << 8)
>> +#define USDHC_VENDOR_SPEC               0xc0
>> +#define USDHC_IMX_FRC_SDCLK_ON          (1 << 8)
>>
>> -#define ESDHC_DLL_CTRL                  0x60
>> +#define USDHC_DLL_CTRL                  0x60
>>
>> -#define ESDHC_TUNING_CTRL               0xcc
>> -#define ESDHC_TUNE_CTRL_STATUS          0x68
>> -#define ESDHC_WTMK_LVL                  0x44
>> +#define USDHC_TUNING_CTRL               0xcc
>> +#define USDHC_TUNE_CTRL_STATUS          0x68
>> +#define USDHC_WTMK_LVL                  0x44
>>
>>  /* Undocumented register used by guests working around erratum ERR004536 */
>> -#define ESDHC_UNDOCUMENTED_REG27        0x6c
>> +#define USDHC_UNDOCUMENTED_REG27        0x6c
>>
>> -#define ESDHC_CTRL_4BITBUS              (0x1 << 1)
>> -#define ESDHC_CTRL_8BITBUS              (0x2 << 1)
>> +#define USDHC_CTRL_4BITBUS              (0x1 << 1)
>> +#define USDHC_CTRL_8BITBUS              (0x2 << 1)
>>
>> -#define ESDHC_PRNSTS_SDSTB              (1 << 3)
>> +#define USDHC_PRNSTS_SDSTB              (1 << 3)
>>
>>  static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
>>  {
>> @@ -1615,11 +1615,11 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
>>          hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3);
>>
>>          if (s->hostctl1 & SDHC_CTRL_8BITBUS) {
>> -            hostctl1 |= ESDHC_CTRL_8BITBUS;
>> +            hostctl1 |= USDHC_CTRL_8BITBUS;
>>          }
>>
>>          if (s->hostctl1 & SDHC_CTRL_4BITBUS) {
>> -            hostctl1 |= ESDHC_CTRL_4BITBUS;
>> +            hostctl1 |= USDHC_CTRL_4BITBUS;
>>          }
>>
>>          ret  = hostctl1;
>> @@ -1630,21 +1630,21 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
>>
>>      case SDHC_PRNSTS:
>>          /* Add SDSTB (SD Clock Stable) bit to PRNSTS */
>> -        ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB;
>> +        ret = sdhci_read(opaque, offset, size) & ~USDHC_PRNSTS_SDSTB;
>>          if (s->clkcon & SDHC_CLOCK_INT_STABLE) {
>> -            ret |= ESDHC_PRNSTS_SDSTB;
>> +            ret |= USDHC_PRNSTS_SDSTB;
>>          }
>>          break;
>>
>> -    case ESDHC_VENDOR_SPEC:
>> +    case USDHC_VENDOR_SPEC:
>>          ret = s->vendor_spec;
>>          break;
>> -    case ESDHC_DLL_CTRL:
>> -    case ESDHC_TUNE_CTRL_STATUS:
>> -    case ESDHC_UNDOCUMENTED_REG27:
>> -    case ESDHC_TUNING_CTRL:
>> -    case ESDHC_MIX_CTRL:
>> -    case ESDHC_WTMK_LVL:
>> +    case USDHC_DLL_CTRL:
>> +    case USDHC_TUNE_CTRL_STATUS:
>> +    case USDHC_UNDOCUMENTED_REG27:
>> +    case USDHC_TUNING_CTRL:
>> +    case USDHC_MIX_CTRL:
>> +    case USDHC_WTMK_LVL:
>>          ret = 0;
>>          break;
>>      }
>> @@ -1660,18 +1660,18 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
>>      uint32_t value = (uint32_t)val;
>>
>>      switch (offset) {
>> -    case ESDHC_DLL_CTRL:
>> -    case ESDHC_TUNE_CTRL_STATUS:
>> -    case ESDHC_UNDOCUMENTED_REG27:
>> -    case ESDHC_TUNING_CTRL:
>> -    case ESDHC_WTMK_LVL:
>> +    case USDHC_DLL_CTRL:
>> +    case USDHC_TUNE_CTRL_STATUS:
>> +    case USDHC_UNDOCUMENTED_REG27:
>> +    case USDHC_TUNING_CTRL:
>> +    case USDHC_WTMK_LVL:
>>          break;
>>
>> -    case ESDHC_VENDOR_SPEC:
>> +    case USDHC_VENDOR_SPEC:
>>          s->vendor_spec = value;
>>          switch (s->vendor) {
>>          case SDHCI_VENDOR_IMX:
>> -            if (value & ESDHC_IMX_FRC_SDCLK_ON) {
>> +            if (value & USDHC_IMX_FRC_SDCLK_ON) {
>>                  s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF;
>>              } else {
>>                  s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF;
>> @@ -1740,12 +1740,12 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
>>           * Second, split "Data Transfer Width" from bits 2 and 1 in to
>>           * bits 5 and 1
>>           */
>> -        if (value & ESDHC_CTRL_8BITBUS) {
>> +        if (value & USDHC_CTRL_8BITBUS) {
>>              hostctl1 |= SDHC_CTRL_8BITBUS;
>>          }
>>
>> -        if (value & ESDHC_CTRL_4BITBUS) {
>> -            hostctl1 |= ESDHC_CTRL_4BITBUS;
>> +        if (value & USDHC_CTRL_4BITBUS) {
>> +            hostctl1 |= USDHC_CTRL_4BITBUS;
>>          }
>>
>>          /*
>> @@ -1768,11 +1768,11 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
>>          sdhci_write(opaque, offset, value, size);
>>          break;
>>
>> -    case ESDHC_MIX_CTRL:
>> +    case USDHC_MIX_CTRL:
>>          /*
>>           * So, when SD/MMC stack in Linux tries to write to "Transfer
>>           * Mode Register", ESDHC i.MX quirk code will translate it
>
>Here I assume ESDHC i.MX means the Linux eSDHC driver for i.MX, so no
>need to replace ESDHC with USDHC?

I see. Prefix with IMX_ then and rename the functions for consistency? Then prefix the MPC ones with MPC_?

>
>> -         * into a write to ESDHC_MIX_CTRL, so we do the opposite in
>> +         * into a write to USDHC_MIX_CTRL, so we do the opposite in
>>           * order to get where we started
>>           *
>>           * Note that Auto CMD23 Enable bit is located in a wrong place
>> --
>
>Overall LGTM:
>Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff mbox series

Patch

diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 6da5e2c781..7a5996caad 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1577,24 +1577,24 @@  static const TypeInfo sdhci_bus_info = {
 
 /* --- qdev i.MX eSDHC --- */
 
-#define ESDHC_MIX_CTRL                  0x48
+#define USDHC_MIX_CTRL                  0x48
 
-#define ESDHC_VENDOR_SPEC               0xc0
-#define ESDHC_IMX_FRC_SDCLK_ON          (1 << 8)
+#define USDHC_VENDOR_SPEC               0xc0
+#define USDHC_IMX_FRC_SDCLK_ON          (1 << 8)
 
-#define ESDHC_DLL_CTRL                  0x60
+#define USDHC_DLL_CTRL                  0x60
 
-#define ESDHC_TUNING_CTRL               0xcc
-#define ESDHC_TUNE_CTRL_STATUS          0x68
-#define ESDHC_WTMK_LVL                  0x44
+#define USDHC_TUNING_CTRL               0xcc
+#define USDHC_TUNE_CTRL_STATUS          0x68
+#define USDHC_WTMK_LVL                  0x44
 
 /* Undocumented register used by guests working around erratum ERR004536 */
-#define ESDHC_UNDOCUMENTED_REG27        0x6c
+#define USDHC_UNDOCUMENTED_REG27        0x6c
 
-#define ESDHC_CTRL_4BITBUS              (0x1 << 1)
-#define ESDHC_CTRL_8BITBUS              (0x2 << 1)
+#define USDHC_CTRL_4BITBUS              (0x1 << 1)
+#define USDHC_CTRL_8BITBUS              (0x2 << 1)
 
-#define ESDHC_PRNSTS_SDSTB              (1 << 3)
+#define USDHC_PRNSTS_SDSTB              (1 << 3)
 
 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
 {
@@ -1615,11 +1615,11 @@  static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
         hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3);
 
         if (s->hostctl1 & SDHC_CTRL_8BITBUS) {
-            hostctl1 |= ESDHC_CTRL_8BITBUS;
+            hostctl1 |= USDHC_CTRL_8BITBUS;
         }
 
         if (s->hostctl1 & SDHC_CTRL_4BITBUS) {
-            hostctl1 |= ESDHC_CTRL_4BITBUS;
+            hostctl1 |= USDHC_CTRL_4BITBUS;
         }
 
         ret  = hostctl1;
@@ -1630,21 +1630,21 @@  static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
 
     case SDHC_PRNSTS:
         /* Add SDSTB (SD Clock Stable) bit to PRNSTS */
-        ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB;
+        ret = sdhci_read(opaque, offset, size) & ~USDHC_PRNSTS_SDSTB;
         if (s->clkcon & SDHC_CLOCK_INT_STABLE) {
-            ret |= ESDHC_PRNSTS_SDSTB;
+            ret |= USDHC_PRNSTS_SDSTB;
         }
         break;
 
-    case ESDHC_VENDOR_SPEC:
+    case USDHC_VENDOR_SPEC:
         ret = s->vendor_spec;
         break;
-    case ESDHC_DLL_CTRL:
-    case ESDHC_TUNE_CTRL_STATUS:
-    case ESDHC_UNDOCUMENTED_REG27:
-    case ESDHC_TUNING_CTRL:
-    case ESDHC_MIX_CTRL:
-    case ESDHC_WTMK_LVL:
+    case USDHC_DLL_CTRL:
+    case USDHC_TUNE_CTRL_STATUS:
+    case USDHC_UNDOCUMENTED_REG27:
+    case USDHC_TUNING_CTRL:
+    case USDHC_MIX_CTRL:
+    case USDHC_WTMK_LVL:
         ret = 0;
         break;
     }
@@ -1660,18 +1660,18 @@  usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
     uint32_t value = (uint32_t)val;
 
     switch (offset) {
-    case ESDHC_DLL_CTRL:
-    case ESDHC_TUNE_CTRL_STATUS:
-    case ESDHC_UNDOCUMENTED_REG27:
-    case ESDHC_TUNING_CTRL:
-    case ESDHC_WTMK_LVL:
+    case USDHC_DLL_CTRL:
+    case USDHC_TUNE_CTRL_STATUS:
+    case USDHC_UNDOCUMENTED_REG27:
+    case USDHC_TUNING_CTRL:
+    case USDHC_WTMK_LVL:
         break;
 
-    case ESDHC_VENDOR_SPEC:
+    case USDHC_VENDOR_SPEC:
         s->vendor_spec = value;
         switch (s->vendor) {
         case SDHCI_VENDOR_IMX:
-            if (value & ESDHC_IMX_FRC_SDCLK_ON) {
+            if (value & USDHC_IMX_FRC_SDCLK_ON) {
                 s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF;
             } else {
                 s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF;
@@ -1740,12 +1740,12 @@  usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
          * Second, split "Data Transfer Width" from bits 2 and 1 in to
          * bits 5 and 1
          */
-        if (value & ESDHC_CTRL_8BITBUS) {
+        if (value & USDHC_CTRL_8BITBUS) {
             hostctl1 |= SDHC_CTRL_8BITBUS;
         }
 
-        if (value & ESDHC_CTRL_4BITBUS) {
-            hostctl1 |= ESDHC_CTRL_4BITBUS;
+        if (value & USDHC_CTRL_4BITBUS) {
+            hostctl1 |= USDHC_CTRL_4BITBUS;
         }
 
         /*
@@ -1768,11 +1768,11 @@  usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
         sdhci_write(opaque, offset, value, size);
         break;
 
-    case ESDHC_MIX_CTRL:
+    case USDHC_MIX_CTRL:
         /*
          * So, when SD/MMC stack in Linux tries to write to "Transfer
          * Mode Register", ESDHC i.MX quirk code will translate it
-         * into a write to ESDHC_MIX_CTRL, so we do the opposite in
+         * into a write to USDHC_MIX_CTRL, so we do the opposite in
          * order to get where we started
          *
          * Note that Auto CMD23 Enable bit is located in a wrong place