| Message ID | 20220915152520.21948-5-shentey@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ppc/e500: Add support for two types of flash, cleanup | expand |
On Thu, Sep 15, 2022 at 11:29 PM Bernhard Beschow <shentey@gmail.com> wrote: > > Models the real device more closely. Please describe the source (e.g.: I assume it's MPC8544DS board manual or something like that?) that describe such memory map for the platform bus. Is this the eLBC bus range that includes the NOR flash device? > > Signed-off-by: Bernhard Beschow <shentey@gmail.com> > --- > hw/ppc/mpc8544ds.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c > index 81177505f0..cd6cd04bef 100644 > --- a/hw/ppc/mpc8544ds.c > +++ b/hw/ppc/mpc8544ds.c > @@ -14,6 +14,7 @@ > #include "sysemu/device_tree.h" > #include "hw/ppc/openpic.h" > #include "qemu/error-report.h" > +#include "qemu/units.h" > #include "cpu.h" > > static void mpc8544ds_fixup_devtree(void *fdt) > @@ -45,6 +46,11 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data) > pmc->pci_nr_slots = 2; > pmc->fixup_devtree = mpc8544ds_fixup_devtree; > pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20; > + pmc->has_platform_bus = true; > + pmc->platform_bus_base = 0xEC000000ULL; > + pmc->platform_bus_size = 128 * MiB; > + pmc->platform_bus_first_irq = 5; > + pmc->platform_bus_num_irqs = 10; > pmc->ccsrbar_base = 0xE0000000ULL; > pmc->pci_mmio_base = 0xC0000000ULL; > pmc->pci_mmio_bus_base = 0xC0000000ULL; > -- Regards, Bin
Am 16. September 2022 06:15:53 UTC schrieb Bin Meng <bmeng.cn@gmail.com>: >On Thu, Sep 15, 2022 at 11:29 PM Bernhard Beschow <shentey@gmail.com> wrote: >> >> Models the real device more closely. > >Please describe the source (e.g.: I assume it's MPC8544DS board manual >or something like that?) that describe such memory map for the >platform bus. > >Is this the eLBC bus range that includes the NOR flash device? Good point. My numbers come from a different board. I'll fix them according to the mpc8544ds.dts in the Linux tree. This will leave an eLBC memory window of just 8MB while my proprietary load needs 64MB. My proprietary load doesn't seem to have 64 bit physical memory support so I can't use e500plat either. Any suggestions? Best regards, Bernhard > >> >> Signed-off-by: Bernhard Beschow <shentey@gmail.com> >> --- >> hw/ppc/mpc8544ds.c | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c >> index 81177505f0..cd6cd04bef 100644 >> --- a/hw/ppc/mpc8544ds.c >> +++ b/hw/ppc/mpc8544ds.c >> @@ -14,6 +14,7 @@ >> #include "sysemu/device_tree.h" >> #include "hw/ppc/openpic.h" >> #include "qemu/error-report.h" >> +#include "qemu/units.h" >> #include "cpu.h" >> >> static void mpc8544ds_fixup_devtree(void *fdt) >> @@ -45,6 +46,11 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data) >> pmc->pci_nr_slots = 2; >> pmc->fixup_devtree = mpc8544ds_fixup_devtree; >> pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20; >> + pmc->has_platform_bus = true; >> + pmc->platform_bus_base = 0xEC000000ULL; >> + pmc->platform_bus_size = 128 * MiB; >> + pmc->platform_bus_first_irq = 5; >> + pmc->platform_bus_num_irqs = 10; >> pmc->ccsrbar_base = 0xE0000000ULL; >> pmc->pci_mmio_base = 0xC0000000ULL; >> pmc->pci_mmio_bus_base = 0xC0000000ULL; >> -- > >Regards, >Bin
Hi Bernhard, On Sat, Sep 17, 2022 at 1:19 AM Bernhard Beschow <shentey@gmail.com> wrote: > > Am 16. September 2022 06:15:53 UTC schrieb Bin Meng <bmeng.cn@gmail.com>: > >On Thu, Sep 15, 2022 at 11:29 PM Bernhard Beschow <shentey@gmail.com> wrote: > >> > >> Models the real device more closely. > > > >Please describe the source (e.g.: I assume it's MPC8544DS board manual > >or something like that?) that describe such memory map for the > >platform bus. > > > >Is this the eLBC bus range that includes the NOR flash device? > > Good point. My numbers come from a different board. I'll fix them according to the mpc8544ds.dts in the Linux tree. > > This will leave an eLBC memory window of just 8MB while my proprietary load needs 64MB. My proprietary load doesn't seem to have 64 bit physical memory support so I can't use e500plat either. Any suggestions? > Currently QEMU does not model the eLBC registers so these memory regions have to be hardcoded, unfortunately. Once we support eLBC memory map completely I think we can remove such limitations by having QEMU dynamically create the memory map per programmed values. I guess you have to create another machine for your board at this point. Regards, Bin
diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c index 81177505f0..cd6cd04bef 100644 --- a/hw/ppc/mpc8544ds.c +++ b/hw/ppc/mpc8544ds.c @@ -14,6 +14,7 @@ #include "sysemu/device_tree.h" #include "hw/ppc/openpic.h" #include "qemu/error-report.h" +#include "qemu/units.h" #include "cpu.h" static void mpc8544ds_fixup_devtree(void *fdt) @@ -45,6 +46,11 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data) pmc->pci_nr_slots = 2; pmc->fixup_devtree = mpc8544ds_fixup_devtree; pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20; + pmc->has_platform_bus = true; + pmc->platform_bus_base = 0xEC000000ULL; + pmc->platform_bus_size = 128 * MiB; + pmc->platform_bus_first_irq = 5; + pmc->platform_bus_num_irqs = 10; pmc->ccsrbar_base = 0xE0000000ULL; pmc->pci_mmio_base = 0xC0000000ULL; pmc->pci_mmio_bus_base = 0xC0000000ULL;
Models the real device more closely. Signed-off-by: Bernhard Beschow <shentey@gmail.com> --- hw/ppc/mpc8544ds.c | 6 ++++++ 1 file changed, 6 insertions(+)