[v2,10/16] rt2x00: add TX LOFT calibration for MT7620

Message ID	dc196a577619af47eb759099e7a7cdbda9f7ce5f.1663431288.git.daniel@makrotopia.org (mailing list archive)
State	Superseded
Delegated to:	Kalle Valo
Headers	show Return-Path: <linux-wireless-owner@kernel.org> Date: Sat, 17 Sep 2022 17:47:50 +0100 From: Daniel Golle <daniel@makrotopia.org> To: linux-wireless@vger.kernel.org, Stanislaw Gruszka <stf_xl@wp.pl>, Helmut Schaa <helmut.schaa@googlemail.com> Cc: Kalle Valo <kvalo@kernel.org>, "David S. Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Johannes Berg <johannes.berg@intel.com> Subject: [PATCH v2 10/16] rt2x00: add TX LOFT calibration for MT7620 Message-ID: <dc196a577619af47eb759099e7a7cdbda9f7ce5f.1663431288.git.daniel@makrotopia.org> References: <cover.1663431288.git.daniel@makrotopia.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <cover.1663431288.git.daniel@makrotopia.org> Precedence: bulk
Series	rt2x00: OpenWrt patches improving MT7620 \| expand [v2,00/16] rt2x00: OpenWrt patches improving MT7620 [v2,01/16] rt2x00: define RF5592 in init_eeprom routine [v2,02/16] rt2x00: add throughput LED trigger [v2,03/16] rt2x00: add support for external PA on MT7620 [v2,04/16] rt2x00: move up and reuse busy wait functions [v2,05/16] rt2x00: add RF self TXDC calibration for MT7620 [v2,06/16] rt2x00: add r calibration for MT7620 [v2,07/16] rt2x00: add RXDCOC calibration for MT7620 [v2,08/16] rt2x00: add RXIQ calibration for MT7620 [v2,09/16] rt2x00: don't run Rt5592 IQ calibration on MT7620 [v2,10/16] rt2x00: add TX LOFT calibration for MT7620 [v2,11/16] rt2x00: move helper functions up in file [v2,12/16] rt2x00: fix HT20/HT40 bandwidth switch on MT7620 [v2,13/16] rt2x00: set correct TX_SW_CFG1 MAC register for MT7620 [v2,14/16] rt2x00: set VGC gain for both chains of MT7620 [v2,15/16] rt2x00: set SoC wmac clock register [v2,16/16] rt2x00: correctly set BBP register 86 for MT7620

Message ID

dc196a577619af47eb759099e7a7cdbda9f7ce5f.1663431288.git.daniel@makrotopia.org (mailing list archive)

State

Superseded

Delegated to:

Kalle Valo

Headers

Date: Sat, 17 Sep 2022 17:47:50 +0100
From: Daniel Golle <daniel@makrotopia.org>
To: linux-wireless@vger.kernel.org, Stanislaw Gruszka <stf_xl@wp.pl>,
        Helmut Schaa <helmut.schaa@googlemail.com>
Cc: Kalle Valo <kvalo@kernel.org>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Johannes Berg <johannes.berg@intel.com>
Subject: [PATCH v2 10/16] rt2x00: add TX LOFT calibration for MT7620
Message-ID: 
 <dc196a577619af47eb759099e7a7cdbda9f7ce5f.1663431288.git.daniel@makrotopia.org>
References: <cover.1663431288.git.daniel@makrotopia.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Disposition: inline
Content-Transfer-Encoding: 8bit
In-Reply-To: <cover.1663431288.git.daniel@makrotopia.org>
Precedence: bulk

Series

rt2x00: OpenWrt patches improving MT7620 | expand

Commit Message

Daniel Golle Sept. 17, 2022, 4:47 p.m. UTC

From: Tomislav Požega <pozega.tomislav@gmail.com>

Add TX LOFT calibration from mtk driver.

Signed-off-by: Tomislav Požega <pozega.tomislav@gmail.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
v2: use helper functions, make tables static const, remove useless
    debug prints

 .../net/wireless/ralink/rt2x00/rt2800lib.c    | 902 ++++++++++++++++++
 .../net/wireless/ralink/rt2x00/rt2800lib.h    |  10 +
 2 files changed, 912 insertions(+)

Comments

kernel test robot Sept. 17, 2022, 7:22 p.m. UTC | #1

Hi Daniel,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on wireless-next/main]
[also build test WARNING on wireless/main linus/master v6.0-rc5 next-20220916]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Daniel-Golle/rt2x00-OpenWrt-patches-improving-MT7620/20220918-005109
base:   https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next.git main
config: m68k-allyesconfig
compiler: m68k-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/40cb92749cf8545acfa03c180c973181abed168c
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Daniel-Golle/rt2x00-OpenWrt-patches-improving-MT7620/20220918-005109
        git checkout 40cb92749cf8545acfa03c180c973181abed168c
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=m68k SHELL=/bin/bash drivers/net/wireless/ralink/rt2x00/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/net/wireless/ralink/rt2x00/rt2800lib.c:9509:6: warning: no previous prototype for 'rt2800_loft_iq_calibration' [-Wmissing-prototypes]
    9509 | void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
         |      ^~~~~~~~~~~~~~~~~~~~~~~~~~


vim +/rt2800_loft_iq_calibration +9509 drivers/net/wireless/ralink/rt2x00/rt2800lib.c

  9508	
> 9509	void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
  9510	{
  9511		struct rf_reg_pair rf_store[CHAIN_NUM][13];
  9512		u32 macorg1 = 0;
  9513		u32 macorg2 = 0;
  9514		u32 macorg3 = 0;
  9515		u32 macorg4 = 0;
  9516		u32 macorg5 = 0;
  9517		u32 orig528 = 0;
  9518		u32 orig52c = 0;
  9519	
  9520		u32 savemacsysctrl = 0;
  9521		u32 macvalue = 0;
  9522		u32 mac13b8 = 0;
  9523		u32 p0 = 0, p1 = 0;
  9524		u32 p0_idx10 = 0, p1_idx10 = 0;
  9525	
  9526		u8 rfvalue;
  9527		u8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2];
  9528		u8 ger[CHAIN_NUM], per[CHAIN_NUM];
  9529	
  9530		u8 vga_gain[] = {14, 14};
  9531		u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0;
  9532		u8 bbpr30, rfb0r39, rfb0r42;
  9533		u8 bbpr1;
  9534		u8 bbpr4;
  9535		u8 bbpr241, bbpr242;
  9536		u8 count_step;
  9537	
  9538		static const u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c};
  9539		static const u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30,
  9540						      0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F};
  9541		static const u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08};
  9542	
  9543		savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  9544		macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
  9545		macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
  9546		macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
  9547		macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
  9548		macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
  9549		mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
  9550		orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
  9551		orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
  9552	
  9553		macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  9554		macvalue &= (~0x04);
  9555		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
  9556	
  9557		if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
  9558			rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
  9559	
  9560		macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  9561		macvalue &= (~0x08);
  9562		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
  9563	
  9564		if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
  9565			rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
  9566	
  9567		for (ch_idx = 0; ch_idx < 2; ch_idx++)
  9568			rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
  9569	
  9570		bbpr30 = rt2800_bbp_read(rt2x00dev, 30);
  9571		rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39);
  9572		rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
  9573	
  9574		rt2800_bbp_write(rt2x00dev, 30, 0x1F);
  9575		rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80);
  9576		rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B);
  9577	
  9578		rt2800_bbp_write(rt2x00dev, 23, 0x00);
  9579		rt2800_bbp_write(rt2x00dev, 24, 0x00);
  9580	
  9581		rt2800_setbbptonegenerator(rt2x00dev);
  9582	
  9583		for (ch_idx = 0; ch_idx < 2; ch_idx++) {
  9584			rt2800_bbp_write(rt2x00dev, 23, 0x00);
  9585			rt2800_bbp_write(rt2x00dev, 24, 0x00);
  9586			rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
  9587			rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
  9588			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
  9589			rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
  9590			rt2800_register_write(rt2x00dev, 0x13b8, 0x10);
  9591			udelay(1);
  9592	
  9593			if (ch_idx == 0)
  9594				rt2800_rf_aux_tx0_loopback(rt2x00dev);
  9595			else
  9596				rt2800_rf_aux_tx1_loopback(rt2x00dev);
  9597	
  9598			udelay(1);
  9599	
  9600			if (ch_idx == 0)
  9601				rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
  9602			else
  9603				rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
  9604	
  9605			rt2800_bbp_write(rt2x00dev, 158, 0x05);
  9606			rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9607	
  9608			rt2800_bbp_write(rt2x00dev, 158, 0x01);
  9609			if (ch_idx == 0)
  9610				rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9611			else
  9612				rt2800_bbp_write(rt2x00dev, 159, 0x01);
  9613	
  9614			vga_gain[ch_idx] = 18;
  9615			for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
  9616				rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]);
  9617				rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]);
  9618	
  9619				macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3);
  9620				macvalue &= (~0x0000F1F1);
  9621				macvalue |= (rf_gain[rf_alc_idx] << 4);
  9622				macvalue |= (rf_gain[rf_alc_idx] << 12);
  9623				rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue);
  9624				macvalue = (0x0000F1F1);
  9625				rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue);
  9626	
  9627				if (rf_alc_idx == 0) {
  9628					rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21);
  9629					for (; vga_gain[ch_idx] > 0;
  9630					     vga_gain[ch_idx] = vga_gain[ch_idx] - 2) {
  9631						rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
  9632						rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
  9633						rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
  9634						rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
  9635						rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
  9636						p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
  9637						rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21);
  9638						p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
  9639						rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1);
  9640						if ((p0 < 7000 * 7000) && (p1 < (7000 * 7000)))
  9641							break;
  9642					}
  9643	
  9644					rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
  9645					rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
  9646	
  9647					rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
  9648						   rfvga_gain_table[vga_gain[ch_idx]]);
  9649	
  9650					if (vga_gain[ch_idx] < 0)
  9651						vga_gain[ch_idx] = 0;
  9652				}
  9653	
  9654				rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
  9655	
  9656				rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
  9657				rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
  9658	
  9659				rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result);
  9660			}
  9661		}
  9662	
  9663		for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
  9664			for (idx = 0; idx < 4; idx++) {
  9665				rt2800_bbp_write(rt2x00dev, 158, 0xB0);
  9666				bbp = (idx << 2) + rf_alc_idx;
  9667				rt2800_bbp_write(rt2x00dev, 159, bbp);
  9668				rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp);
  9669	
  9670				rt2800_bbp_write(rt2x00dev, 158, 0xb1);
  9671				bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00];
  9672				bbp = bbp & 0x3F;
  9673				rt2800_bbp_write(rt2x00dev, 159, bbp);
  9674				rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp);
  9675	
  9676				rt2800_bbp_write(rt2x00dev, 158, 0xb2);
  9677				bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01];
  9678				bbp = bbp & 0x3F;
  9679				rt2800_bbp_write(rt2x00dev, 159, bbp);
  9680				rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp);
  9681	
  9682				rt2800_bbp_write(rt2x00dev, 158, 0xb8);
  9683				bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00];
  9684				bbp = bbp & 0x3F;
  9685				rt2800_bbp_write(rt2x00dev, 159, bbp);
  9686				rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp);
  9687	
  9688				rt2800_bbp_write(rt2x00dev, 158, 0xb9);
  9689				bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01];
  9690				bbp = bbp & 0x3F;
  9691				rt2800_bbp_write(rt2x00dev, 159, bbp);
  9692				rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp);
  9693			}
  9694		}
  9695	
  9696		rt2800_bbp_write(rt2x00dev, 23, 0x00);
  9697		rt2800_bbp_write(rt2x00dev, 24, 0x00);
  9698	
  9699		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
  9700	
  9701		rt2800_bbp_write(rt2x00dev, 158, 0x00);
  9702		rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9703	
  9704		bbp = 0x00;
  9705		rt2800_bbp_write(rt2x00dev, 244, 0x00);
  9706	
  9707		rt2800_bbp_write(rt2x00dev, 21, 0x01);
  9708		udelay(1);
  9709		rt2800_bbp_write(rt2x00dev, 21, 0x00);
  9710	
  9711		rt2800_rf_configrecover(rt2x00dev, rf_store);
  9712	
  9713		rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
  9714		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
  9715		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
  9716		rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
  9717		rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
  9718		udelay(1);
  9719		rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
  9720		rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
  9721		rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
  9722		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
  9723		rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528);
  9724		rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c);
  9725		rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
  9726	
  9727		savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  9728		macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
  9729		macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
  9730		macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
  9731		macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
  9732		macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
  9733	
  9734		bbpr1 = rt2800_bbp_read(rt2x00dev, 1);
  9735		bbpr4 = rt2800_bbp_read(rt2x00dev, 4);
  9736		bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
  9737		bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
  9738		mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
  9739	
  9740		macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  9741		macvalue &= (~0x04);
  9742		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
  9743	
  9744		if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
  9745			rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
  9746	
  9747		macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  9748		macvalue &= (~0x08);
  9749		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
  9750	
  9751		if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
  9752			rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
  9753	
  9754		if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
  9755			rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101);
  9756			rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
  9757		}
  9758	
  9759		rt2800_bbp_write(rt2x00dev, 23, 0x00);
  9760		rt2800_bbp_write(rt2x00dev, 24, 0x00);
  9761	
  9762		if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
  9763			rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18));
  9764			rt2800_bbp_write(rt2x00dev, 21, 0x01);
  9765			udelay(1);
  9766			rt2800_bbp_write(rt2x00dev, 21, 0x00);
  9767	
  9768			rt2800_bbp_write(rt2x00dev, 241, 0x14);
  9769			rt2800_bbp_write(rt2x00dev, 242, 0x80);
  9770			rt2800_bbp_write(rt2x00dev, 244, 0x31);
  9771		} else {
  9772			rt2800_setbbptonegenerator(rt2x00dev);
  9773		}
  9774	
  9775		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
  9776		rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
  9777		udelay(1);
  9778	
  9779		rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
  9780	
  9781		if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
  9782			rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000);
  9783			rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
  9784		}
  9785	
  9786		rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010);
  9787	
  9788		for (ch_idx = 0; ch_idx < 2; ch_idx++)
  9789			rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
  9790	
  9791		rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B);
  9792		rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B);
  9793	
  9794		rt2800_bbp_write(rt2x00dev, 158, 0x03);
  9795		rt2800_bbp_write(rt2x00dev, 159, 0x60);
  9796		rt2800_bbp_write(rt2x00dev, 158, 0xB0);
  9797		rt2800_bbp_write(rt2x00dev, 159, 0x80);
  9798	
  9799		for (ch_idx = 0; ch_idx < 2; ch_idx++) {
  9800			rt2800_bbp_write(rt2x00dev, 23, 0x00);
  9801			rt2800_bbp_write(rt2x00dev, 24, 0x00);
  9802	
  9803			if (ch_idx == 0) {
  9804				rt2800_bbp_write(rt2x00dev, 158, 0x01);
  9805				rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9806				if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
  9807					bbp = bbpr1 & (~0x18);
  9808					bbp = bbp | 0x00;
  9809					rt2800_bbp_write(rt2x00dev, 1, bbp);
  9810				}
  9811				rt2800_rf_aux_tx0_loopback(rt2x00dev);
  9812				rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
  9813			} else {
  9814				rt2800_bbp_write(rt2x00dev, 158, 0x01);
  9815				rt2800_bbp_write(rt2x00dev, 159, 0x01);
  9816				if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
  9817					bbp = bbpr1 & (~0x18);
  9818					bbp = bbp | 0x08;
  9819					rt2800_bbp_write(rt2x00dev, 1, bbp);
  9820				}
  9821				rt2800_rf_aux_tx1_loopback(rt2x00dev);
  9822				rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
  9823			}
  9824	
  9825			rt2800_bbp_write(rt2x00dev, 158, 0x05);
  9826			rt2800_bbp_write(rt2x00dev, 159, 0x04);
  9827	
  9828			bbp = (ch_idx == 0) ? 0x28 : 0x46;
  9829			rt2800_bbp_write(rt2x00dev, 158, bbp);
  9830			rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9831	
  9832			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
  9833				rt2800_bbp_write(rt2x00dev, 23, 0x06);
  9834				rt2800_bbp_write(rt2x00dev, 24, 0x06);
  9835				count_step = 1;
  9836			} else {
  9837				rt2800_bbp_write(rt2x00dev, 23, 0x1F);
  9838				rt2800_bbp_write(rt2x00dev, 24, 0x1F);
  9839				count_step = 2;
  9840			}
  9841	
  9842			for (; vga_gain[ch_idx] < 19; vga_gain[ch_idx] = (vga_gain[ch_idx] + count_step)) {
  9843				rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
  9844				rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
  9845				rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
  9846	
  9847				bbp = (ch_idx == 0) ? 0x29 : 0x47;
  9848				rt2800_bbp_write(rt2x00dev, 158, bbp);
  9849				rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9850				p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
  9851				if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
  9852					p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
  9853	
  9854				bbp = (ch_idx == 0) ? 0x29 : 0x47;
  9855				rt2800_bbp_write(rt2x00dev, 158, bbp);
  9856				rt2800_bbp_write(rt2x00dev, 159, 0x21);
  9857				p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
  9858				if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags))
  9859					p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
  9860	
  9861				rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1);
  9862	
  9863				if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
  9864					rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10);
  9865					if ((p0_idx10 > 7000 * 7000) || (p1_idx10 > 7000 * 7000)) {
  9866						if (vga_gain[ch_idx] != 0)
  9867							vga_gain[ch_idx] = vga_gain[ch_idx] - 1;
  9868						break;
  9869					}
  9870				}
  9871	
  9872				if ((p0 > 2500 * 2500) || (p1 > 2500 * 2500))
  9873					break;
  9874			}
  9875	
  9876			if (vga_gain[ch_idx] > 18)
  9877				vga_gain[ch_idx] = 18;
  9878			rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
  9879				   rfvga_gain_table[vga_gain[ch_idx]]);
  9880	
  9881			bbp = (ch_idx == 0) ? 0x29 : 0x47;
  9882			rt2800_bbp_write(rt2x00dev, 158, bbp);
  9883			rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9884	
  9885			rt2800_iq_search(rt2x00dev, ch_idx, ger, per);
  9886		}
  9887	
  9888		rt2800_bbp_write(rt2x00dev, 23, 0x00);
  9889		rt2800_bbp_write(rt2x00dev, 24, 0x00);
  9890		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
  9891	
  9892		rt2800_bbp_write(rt2x00dev, 158, 0x28);
  9893		bbp = ger[CHAIN_0] & 0x0F;
  9894		rt2800_bbp_write(rt2x00dev, 159, bbp);
  9895	
  9896		rt2800_bbp_write(rt2x00dev, 158, 0x29);
  9897		bbp = per[CHAIN_0] & 0x3F;
  9898		rt2800_bbp_write(rt2x00dev, 159, bbp);
  9899	
  9900		rt2800_bbp_write(rt2x00dev, 158, 0x46);
  9901		bbp = ger[CHAIN_1] & 0x0F;
  9902		rt2800_bbp_write(rt2x00dev, 159, bbp);
  9903	
  9904		rt2800_bbp_write(rt2x00dev, 158, 0x47);
  9905		bbp = per[CHAIN_1] & 0x3F;
  9906		rt2800_bbp_write(rt2x00dev, 159, bbp);
  9907	
  9908		if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
  9909			rt2800_bbp_write(rt2x00dev, 1, bbpr1);
  9910			rt2800_bbp_write(rt2x00dev, 241, bbpr241);
  9911			rt2800_bbp_write(rt2x00dev, 242, bbpr242);
  9912		}
  9913		rt2800_bbp_write(rt2x00dev, 244, 0x00);
  9914	
  9915		rt2800_bbp_write(rt2x00dev, 158, 0x00);
  9916		rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9917		rt2800_bbp_write(rt2x00dev, 158, 0xB0);
  9918		rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9919	
  9920		rt2800_bbp_write(rt2x00dev, 30, bbpr30);
  9921		rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39);
  9922		rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
  9923	
  9924		if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
  9925			rt2800_bbp_write(rt2x00dev, 4, bbpr4);
  9926	
  9927		rt2800_bbp_write(rt2x00dev, 21, 0x01);
  9928		udelay(1);
  9929		rt2800_bbp_write(rt2x00dev, 21, 0x00);
  9930	
  9931		rt2800_rf_configrecover(rt2x00dev, rf_store);
  9932	
  9933		rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
  9934		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
  9935		rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
  9936		rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
  9937		udelay(1);
  9938		rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
  9939		rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
  9940		rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
  9941		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
  9942		rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
  9943	}
  9944

kernel test robot Sept. 18, 2022, 3:08 p.m. UTC | #2

Hi Daniel,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on wireless-next/main]
[also build test WARNING on wireless/main linus/master v6.0-rc5 next-20220916]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Daniel-Golle/rt2x00-OpenWrt-patches-improving-MT7620/20220918-005109
base:   https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next.git main
config: i386-allmodconfig (https://download.01.org/0day-ci/archive/20220918/202209182215.MtqzOalX-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/40cb92749cf8545acfa03c180c973181abed168c
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Daniel-Golle/rt2x00-OpenWrt-patches-improving-MT7620/20220918-005109
        git checkout 40cb92749cf8545acfa03c180c973181abed168c
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/cpuidle/governors/ drivers/net/ethernet/mellanox/mlx5/core/ drivers/net/wireless/ralink/rt2x00/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/net/wireless/ralink/rt2x00/rt2800lib.c:9509:6: warning: no previous prototype for function 'rt2800_loft_iq_calibration' [-Wmissing-prototypes]
   void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
        ^
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:9509:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
   ^
   static 
   1 warning generated.


vim +/rt2800_loft_iq_calibration +9509 drivers/net/wireless/ralink/rt2x00/rt2800lib.c

  9508	
> 9509	void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
  9510	{
  9511		struct rf_reg_pair rf_store[CHAIN_NUM][13];
  9512		u32 macorg1 = 0;
  9513		u32 macorg2 = 0;
  9514		u32 macorg3 = 0;
  9515		u32 macorg4 = 0;
  9516		u32 macorg5 = 0;
  9517		u32 orig528 = 0;
  9518		u32 orig52c = 0;
  9519	
  9520		u32 savemacsysctrl = 0;
  9521		u32 macvalue = 0;
  9522		u32 mac13b8 = 0;
  9523		u32 p0 = 0, p1 = 0;
  9524		u32 p0_idx10 = 0, p1_idx10 = 0;
  9525	
  9526		u8 rfvalue;
  9527		u8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2];
  9528		u8 ger[CHAIN_NUM], per[CHAIN_NUM];
  9529	
  9530		u8 vga_gain[] = {14, 14};
  9531		u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0;
  9532		u8 bbpr30, rfb0r39, rfb0r42;
  9533		u8 bbpr1;
  9534		u8 bbpr4;
  9535		u8 bbpr241, bbpr242;
  9536		u8 count_step;
  9537	
  9538		static const u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c};
  9539		static const u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30,
  9540						      0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F};
  9541		static const u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08};
  9542	
  9543		savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  9544		macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
  9545		macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
  9546		macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
  9547		macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
  9548		macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
  9549		mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
  9550		orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
  9551		orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
  9552	
  9553		macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  9554		macvalue &= (~0x04);
  9555		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
  9556	
  9557		if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
  9558			rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
  9559	
  9560		macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  9561		macvalue &= (~0x08);
  9562		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
  9563	
  9564		if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
  9565			rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
  9566	
  9567		for (ch_idx = 0; ch_idx < 2; ch_idx++)
  9568			rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
  9569	
  9570		bbpr30 = rt2800_bbp_read(rt2x00dev, 30);
  9571		rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39);
  9572		rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
  9573	
  9574		rt2800_bbp_write(rt2x00dev, 30, 0x1F);
  9575		rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80);
  9576		rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B);
  9577	
  9578		rt2800_bbp_write(rt2x00dev, 23, 0x00);
  9579		rt2800_bbp_write(rt2x00dev, 24, 0x00);
  9580	
  9581		rt2800_setbbptonegenerator(rt2x00dev);
  9582	
  9583		for (ch_idx = 0; ch_idx < 2; ch_idx++) {
  9584			rt2800_bbp_write(rt2x00dev, 23, 0x00);
  9585			rt2800_bbp_write(rt2x00dev, 24, 0x00);
  9586			rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
  9587			rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
  9588			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
  9589			rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
  9590			rt2800_register_write(rt2x00dev, 0x13b8, 0x10);
  9591			udelay(1);
  9592	
  9593			if (ch_idx == 0)
  9594				rt2800_rf_aux_tx0_loopback(rt2x00dev);
  9595			else
  9596				rt2800_rf_aux_tx1_loopback(rt2x00dev);
  9597	
  9598			udelay(1);
  9599	
  9600			if (ch_idx == 0)
  9601				rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
  9602			else
  9603				rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
  9604	
  9605			rt2800_bbp_write(rt2x00dev, 158, 0x05);
  9606			rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9607	
  9608			rt2800_bbp_write(rt2x00dev, 158, 0x01);
  9609			if (ch_idx == 0)
  9610				rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9611			else
  9612				rt2800_bbp_write(rt2x00dev, 159, 0x01);
  9613	
  9614			vga_gain[ch_idx] = 18;
  9615			for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
  9616				rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]);
  9617				rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]);
  9618	
  9619				macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3);
  9620				macvalue &= (~0x0000F1F1);
  9621				macvalue |= (rf_gain[rf_alc_idx] << 4);
  9622				macvalue |= (rf_gain[rf_alc_idx] << 12);
  9623				rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue);
  9624				macvalue = (0x0000F1F1);
  9625				rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue);
  9626	
  9627				if (rf_alc_idx == 0) {
  9628					rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21);
  9629					for (; vga_gain[ch_idx] > 0;
  9630					     vga_gain[ch_idx] = vga_gain[ch_idx] - 2) {
  9631						rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
  9632						rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
  9633						rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
  9634						rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
  9635						rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
  9636						p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
  9637						rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21);
  9638						p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
  9639						rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1);
  9640						if ((p0 < 7000 * 7000) && (p1 < (7000 * 7000)))
  9641							break;
  9642					}
  9643	
  9644					rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
  9645					rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
  9646	
  9647					rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
  9648						   rfvga_gain_table[vga_gain[ch_idx]]);
  9649	
  9650					if (vga_gain[ch_idx] < 0)
  9651						vga_gain[ch_idx] = 0;
  9652				}
  9653	
  9654				rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
  9655	
  9656				rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
  9657				rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
  9658	
  9659				rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result);
  9660			}
  9661		}
  9662	
  9663		for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
  9664			for (idx = 0; idx < 4; idx++) {
  9665				rt2800_bbp_write(rt2x00dev, 158, 0xB0);
  9666				bbp = (idx << 2) + rf_alc_idx;
  9667				rt2800_bbp_write(rt2x00dev, 159, bbp);
  9668				rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp);
  9669	
  9670				rt2800_bbp_write(rt2x00dev, 158, 0xb1);
  9671				bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00];
  9672				bbp = bbp & 0x3F;
  9673				rt2800_bbp_write(rt2x00dev, 159, bbp);
  9674				rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp);
  9675	
  9676				rt2800_bbp_write(rt2x00dev, 158, 0xb2);
  9677				bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01];
  9678				bbp = bbp & 0x3F;
  9679				rt2800_bbp_write(rt2x00dev, 159, bbp);
  9680				rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp);
  9681	
  9682				rt2800_bbp_write(rt2x00dev, 158, 0xb8);
  9683				bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00];
  9684				bbp = bbp & 0x3F;
  9685				rt2800_bbp_write(rt2x00dev, 159, bbp);
  9686				rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp);
  9687	
  9688				rt2800_bbp_write(rt2x00dev, 158, 0xb9);
  9689				bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01];
  9690				bbp = bbp & 0x3F;
  9691				rt2800_bbp_write(rt2x00dev, 159, bbp);
  9692				rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp);
  9693			}
  9694		}
  9695	
  9696		rt2800_bbp_write(rt2x00dev, 23, 0x00);
  9697		rt2800_bbp_write(rt2x00dev, 24, 0x00);
  9698	
  9699		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
  9700	
  9701		rt2800_bbp_write(rt2x00dev, 158, 0x00);
  9702		rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9703	
  9704		bbp = 0x00;
  9705		rt2800_bbp_write(rt2x00dev, 244, 0x00);
  9706	
  9707		rt2800_bbp_write(rt2x00dev, 21, 0x01);
  9708		udelay(1);
  9709		rt2800_bbp_write(rt2x00dev, 21, 0x00);
  9710	
  9711		rt2800_rf_configrecover(rt2x00dev, rf_store);
  9712	
  9713		rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
  9714		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
  9715		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
  9716		rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
  9717		rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
  9718		udelay(1);
  9719		rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
  9720		rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
  9721		rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
  9722		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
  9723		rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528);
  9724		rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c);
  9725		rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
  9726	
  9727		savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  9728		macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
  9729		macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
  9730		macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
  9731		macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
  9732		macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
  9733	
  9734		bbpr1 = rt2800_bbp_read(rt2x00dev, 1);
  9735		bbpr4 = rt2800_bbp_read(rt2x00dev, 4);
  9736		bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
  9737		bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
  9738		mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
  9739	
  9740		macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  9741		macvalue &= (~0x04);
  9742		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
  9743	
  9744		if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
  9745			rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
  9746	
  9747		macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  9748		macvalue &= (~0x08);
  9749		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
  9750	
  9751		if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
  9752			rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
  9753	
  9754		if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
  9755			rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101);
  9756			rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
  9757		}
  9758	
  9759		rt2800_bbp_write(rt2x00dev, 23, 0x00);
  9760		rt2800_bbp_write(rt2x00dev, 24, 0x00);
  9761	
  9762		if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
  9763			rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18));
  9764			rt2800_bbp_write(rt2x00dev, 21, 0x01);
  9765			udelay(1);
  9766			rt2800_bbp_write(rt2x00dev, 21, 0x00);
  9767	
  9768			rt2800_bbp_write(rt2x00dev, 241, 0x14);
  9769			rt2800_bbp_write(rt2x00dev, 242, 0x80);
  9770			rt2800_bbp_write(rt2x00dev, 244, 0x31);
  9771		} else {
  9772			rt2800_setbbptonegenerator(rt2x00dev);
  9773		}
  9774	
  9775		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
  9776		rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
  9777		udelay(1);
  9778	
  9779		rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
  9780	
  9781		if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
  9782			rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000);
  9783			rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
  9784		}
  9785	
  9786		rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010);
  9787	
  9788		for (ch_idx = 0; ch_idx < 2; ch_idx++)
  9789			rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
  9790	
  9791		rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B);
  9792		rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B);
  9793	
  9794		rt2800_bbp_write(rt2x00dev, 158, 0x03);
  9795		rt2800_bbp_write(rt2x00dev, 159, 0x60);
  9796		rt2800_bbp_write(rt2x00dev, 158, 0xB0);
  9797		rt2800_bbp_write(rt2x00dev, 159, 0x80);
  9798	
  9799		for (ch_idx = 0; ch_idx < 2; ch_idx++) {
  9800			rt2800_bbp_write(rt2x00dev, 23, 0x00);
  9801			rt2800_bbp_write(rt2x00dev, 24, 0x00);
  9802	
  9803			if (ch_idx == 0) {
  9804				rt2800_bbp_write(rt2x00dev, 158, 0x01);
  9805				rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9806				if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
  9807					bbp = bbpr1 & (~0x18);
  9808					bbp = bbp | 0x00;
  9809					rt2800_bbp_write(rt2x00dev, 1, bbp);
  9810				}
  9811				rt2800_rf_aux_tx0_loopback(rt2x00dev);
  9812				rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
  9813			} else {
  9814				rt2800_bbp_write(rt2x00dev, 158, 0x01);
  9815				rt2800_bbp_write(rt2x00dev, 159, 0x01);
  9816				if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
  9817					bbp = bbpr1 & (~0x18);
  9818					bbp = bbp | 0x08;
  9819					rt2800_bbp_write(rt2x00dev, 1, bbp);
  9820				}
  9821				rt2800_rf_aux_tx1_loopback(rt2x00dev);
  9822				rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
  9823			}
  9824	
  9825			rt2800_bbp_write(rt2x00dev, 158, 0x05);
  9826			rt2800_bbp_write(rt2x00dev, 159, 0x04);
  9827	
  9828			bbp = (ch_idx == 0) ? 0x28 : 0x46;
  9829			rt2800_bbp_write(rt2x00dev, 158, bbp);
  9830			rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9831	
  9832			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
  9833				rt2800_bbp_write(rt2x00dev, 23, 0x06);
  9834				rt2800_bbp_write(rt2x00dev, 24, 0x06);
  9835				count_step = 1;
  9836			} else {
  9837				rt2800_bbp_write(rt2x00dev, 23, 0x1F);
  9838				rt2800_bbp_write(rt2x00dev, 24, 0x1F);
  9839				count_step = 2;
  9840			}
  9841	
  9842			for (; vga_gain[ch_idx] < 19; vga_gain[ch_idx] = (vga_gain[ch_idx] + count_step)) {
  9843				rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
  9844				rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
  9845				rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
  9846	
  9847				bbp = (ch_idx == 0) ? 0x29 : 0x47;
  9848				rt2800_bbp_write(rt2x00dev, 158, bbp);
  9849				rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9850				p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
  9851				if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
  9852					p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
  9853	
  9854				bbp = (ch_idx == 0) ? 0x29 : 0x47;
  9855				rt2800_bbp_write(rt2x00dev, 158, bbp);
  9856				rt2800_bbp_write(rt2x00dev, 159, 0x21);
  9857				p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
  9858				if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags))
  9859					p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
  9860	
  9861				rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1);
  9862	
  9863				if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
  9864					rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10);
  9865					if ((p0_idx10 > 7000 * 7000) || (p1_idx10 > 7000 * 7000)) {
  9866						if (vga_gain[ch_idx] != 0)
  9867							vga_gain[ch_idx] = vga_gain[ch_idx] - 1;
  9868						break;
  9869					}
  9870				}
  9871	
  9872				if ((p0 > 2500 * 2500) || (p1 > 2500 * 2500))
  9873					break;
  9874			}
  9875	
  9876			if (vga_gain[ch_idx] > 18)
  9877				vga_gain[ch_idx] = 18;
  9878			rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
  9879				   rfvga_gain_table[vga_gain[ch_idx]]);
  9880	
  9881			bbp = (ch_idx == 0) ? 0x29 : 0x47;
  9882			rt2800_bbp_write(rt2x00dev, 158, bbp);
  9883			rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9884	
  9885			rt2800_iq_search(rt2x00dev, ch_idx, ger, per);
  9886		}
  9887	
  9888		rt2800_bbp_write(rt2x00dev, 23, 0x00);
  9889		rt2800_bbp_write(rt2x00dev, 24, 0x00);
  9890		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
  9891	
  9892		rt2800_bbp_write(rt2x00dev, 158, 0x28);
  9893		bbp = ger[CHAIN_0] & 0x0F;
  9894		rt2800_bbp_write(rt2x00dev, 159, bbp);
  9895	
  9896		rt2800_bbp_write(rt2x00dev, 158, 0x29);
  9897		bbp = per[CHAIN_0] & 0x3F;
  9898		rt2800_bbp_write(rt2x00dev, 159, bbp);
  9899	
  9900		rt2800_bbp_write(rt2x00dev, 158, 0x46);
  9901		bbp = ger[CHAIN_1] & 0x0F;
  9902		rt2800_bbp_write(rt2x00dev, 159, bbp);
  9903	
  9904		rt2800_bbp_write(rt2x00dev, 158, 0x47);
  9905		bbp = per[CHAIN_1] & 0x3F;
  9906		rt2800_bbp_write(rt2x00dev, 159, bbp);
  9907	
  9908		if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
  9909			rt2800_bbp_write(rt2x00dev, 1, bbpr1);
  9910			rt2800_bbp_write(rt2x00dev, 241, bbpr241);
  9911			rt2800_bbp_write(rt2x00dev, 242, bbpr242);
  9912		}
  9913		rt2800_bbp_write(rt2x00dev, 244, 0x00);
  9914	
  9915		rt2800_bbp_write(rt2x00dev, 158, 0x00);
  9916		rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9917		rt2800_bbp_write(rt2x00dev, 158, 0xB0);
  9918		rt2800_bbp_write(rt2x00dev, 159, 0x00);
  9919	
  9920		rt2800_bbp_write(rt2x00dev, 30, bbpr30);
  9921		rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39);
  9922		rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
  9923	
  9924		if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
  9925			rt2800_bbp_write(rt2x00dev, 4, bbpr4);
  9926	
  9927		rt2800_bbp_write(rt2x00dev, 21, 0x01);
  9928		udelay(1);
  9929		rt2800_bbp_write(rt2x00dev, 21, 0x00);
  9930	
  9931		rt2800_rf_configrecover(rt2x00dev, rf_store);
  9932	
  9933		rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
  9934		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
  9935		rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
  9936		rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
  9937		udelay(1);
  9938		rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
  9939		rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
  9940		rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
  9941		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
  9942		rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
  9943	}
  9944

kernel test robot Sept. 19, 2022, 4:54 p.m. UTC | #3

Hi Daniel,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on wireless-next/main]
[also build test WARNING on wireless/main linus/master v6.0-rc6 next-20220919]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Daniel-Golle/rt2x00-OpenWrt-patches-improving-MT7620/20220918-005109
base:   https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next.git main
config: x86_64-randconfig-s021-20220919 (https://download.01.org/0day-ci/archive/20220920/202209200029.jYBBo5kD-lkp@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-5) 11.3.0
reproduce:
        # apt-get install sparse
        # sparse version: v0.6.4-39-gce1a6720-dirty
        # https://github.com/intel-lab-lkp/linux/commit/40cb92749cf8545acfa03c180c973181abed168c
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Daniel-Golle/rt2x00-OpenWrt-patches-improving-MT7620/20220918-005109
        git checkout 40cb92749cf8545acfa03c180c973181abed168c
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/net/wireless/ralink/rt2x00/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>

sparse warnings: (new ones prefixed by >>)
>> drivers/net/wireless/ralink/rt2x00/rt2800lib.c:9509:6: sparse: sparse: symbol 'rt2800_loft_iq_calibration' was not declared. Should it be static?
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:10765:39: sparse: sparse: incorrect type in assignment (different base types) @@     expected unsigned int [usertype] @@     got restricted __le32 [usertype] @@
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:10765:39: sparse:     expected unsigned int [usertype]
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:10765:39: sparse:     got restricted __le32 [usertype]
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:10767:43: sparse: sparse: incorrect type in assignment (different base types) @@     expected unsigned int [usertype] @@     got restricted __le32 [usertype] @@
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:10767:43: sparse:     expected unsigned int [usertype]
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:10767:43: sparse:     got restricted __le32 [usertype]
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:10769:43: sparse: sparse: incorrect type in assignment (different base types) @@     expected unsigned int [usertype] @@     got restricted __le32 [usertype] @@
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:10769:43: sparse:     expected unsigned int [usertype]
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:10769:43: sparse:     got restricted __le32 [usertype]
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:10771:43: sparse: sparse: incorrect type in assignment (different base types) @@     expected unsigned int [usertype] @@     got restricted __le32 [usertype] @@
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:10771:43: sparse:     expected unsigned int [usertype]
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:10771:43: sparse:     got restricted __le32 [usertype]

kernel test robot Sept. 19, 2022, 8:18 p.m. UTC | #4

Hi Daniel,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on wireless-next/main]
[also build test WARNING on wireless/main linus/master v6.0-rc6 next-20220919]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Daniel-Golle/rt2x00-OpenWrt-patches-improving-MT7620/20220918-005109
base:   https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next.git main
config: arm-defconfig (https://download.01.org/0day-ci/archive/20220920/202209200402.3TMVPkx4-lkp@intel.com/config)
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 791a7ae1ba3efd6bca96338e10ffde557ba83920)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm cross compiling tool for clang build
        # apt-get install binutils-arm-linux-gnueabi
        # https://github.com/intel-lab-lkp/linux/commit/40cb92749cf8545acfa03c180c973181abed168c
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Daniel-Golle/rt2x00-OpenWrt-patches-improving-MT7620/20220918-005109
        git checkout 40cb92749cf8545acfa03c180c973181abed168c
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/irqchip/ drivers/net/wireless/ralink/rt2x00/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/net/wireless/ralink/rt2x00/rt2800lib.c:9439:15: warning: result of comparison of constant -7 with expression of type 'char' is always false [-Wtautological-constant-out-of-range-compare]
           gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr;
                   ~~~~ ^ ~~~~~
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:9443:15: warning: result of comparison of constant -31 with expression of type 'char' is always false [-Wtautological-constant-out-of-range-compare]
           perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr;
                   ~~~~ ^ ~~~~~
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:9509:6: warning: no previous prototype for function 'rt2800_loft_iq_calibration' [-Wmissing-prototypes]
   void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
        ^
   drivers/net/wireless/ralink/rt2x00/rt2800lib.c:9509:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
   ^
   static 
   3 warnings generated.


vim +/char +9439 drivers/net/wireless/ralink/rt2x00/rt2800lib.c

  9350	
  9351	static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)
  9352	{
  9353		u32 p0 = 0, p1 = 0, pf = 0;
  9354		char perr = 0, gerr = 0, iq_err = 0;
  9355		char pef = 0, gef = 0;
  9356		char psta, pend;
  9357		char gsta, gend;
  9358	
  9359		u8 ibit = 0x20;
  9360		u8 first_search = 0x00, touch_neg_max = 0x00;
  9361		char idx0 = 0, idx1 = 0;
  9362		u8 gop;
  9363		u8 bbp = 0;
  9364		char bidx;
  9365	
  9366		for (bidx = 5; bidx >= 1; bidx--) {
  9367			for (gop = 0; gop < 2; gop++) {
  9368				if (gop == 1 || bidx < 4) {
  9369					if (gop == 0)
  9370						iq_err = gerr;
  9371					else
  9372						iq_err = perr;
  9373	
  9374					first_search = (gop == 0) ? (bidx == 3) : (bidx == 5);
  9375					touch_neg_max = (gop) ? ((iq_err & 0x0F) == 0x08) :
  9376								((iq_err & 0x3F) == 0x20);
  9377	
  9378					if (touch_neg_max) {
  9379						p0 = pf;
  9380						idx0 = iq_err;
  9381					} else {
  9382						idx0 = iq_err - ibit;
  9383						bbp = (ch_idx == 0) ? ((gop == 0) ? 0x28 : 0x29) :
  9384								      ((gop == 0) ? 0x46 : 0x47);
  9385	
  9386						rt2800_bbp_write(rt2x00dev, 158, bbp);
  9387						rt2800_bbp_write(rt2x00dev, 159, idx0);
  9388	
  9389						p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
  9390					}
  9391	
  9392					idx1 = iq_err + (first_search ? 0 : ibit);
  9393					idx1 = (gop == 0) ? (idx1 & 0x0F) : (idx1 & 0x3F);
  9394	
  9395					bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 :
  9396					      (gop == 0) ? 0x46 : 0x47;
  9397	
  9398					rt2800_bbp_write(rt2x00dev, 158, bbp);
  9399					rt2800_bbp_write(rt2x00dev, 159, idx1);
  9400	
  9401					p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
  9402	
  9403					rt2x00_dbg(rt2x00dev,
  9404						   "p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x\n",
  9405						   p0, p1, pf, idx0, idx1, iq_err, gop, ibit);
  9406	
  9407					if (!(!first_search && pf <= p0 && pf < p1)) {
  9408						if (p0 < p1) {
  9409							pf = p0;
  9410							iq_err = idx0;
  9411						} else {
  9412							pf = p1;
  9413							iq_err = idx1;
  9414						}
  9415					}
  9416	
  9417					bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 :
  9418							      (gop == 0) ? 0x46 : 0x47;
  9419	
  9420					rt2800_bbp_write(rt2x00dev, 158, bbp);
  9421					rt2800_bbp_write(rt2x00dev, 159, iq_err);
  9422	
  9423					if (gop == 0)
  9424						gerr = iq_err;
  9425					else
  9426						perr = iq_err;
  9427	
  9428					rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n",
  9429						   pf, gerr & 0x0F, perr & 0x3F);
  9430				}
  9431			}
  9432	
  9433			if (bidx > 0)
  9434				ibit = (ibit >> 1);
  9435		}
  9436		gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F);
  9437		perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F);
  9438	
> 9439		gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr;
  9440		gsta = gerr - 1;
  9441		gend = gerr + 2;
  9442	
  9443		perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr;
  9444		psta = perr - 1;
  9445		pend = perr + 2;
  9446	
  9447		for (gef = gsta; gef <= gend; gef = gef + 1)
  9448			for (pef = psta; pef <= pend; pef = pef + 1) {
  9449				bbp = (ch_idx == 0) ? 0x28 : 0x46;
  9450				rt2800_bbp_write(rt2x00dev, 158, bbp);
  9451				rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F);
  9452	
  9453				bbp = (ch_idx == 0) ? 0x29 : 0x47;
  9454				rt2800_bbp_write(rt2x00dev, 158, bbp);
  9455				rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F);
  9456	
  9457				p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
  9458				if (gef == gsta && pef == psta) {
  9459					pf = p1;
  9460					gerr = gef;
  9461					perr = pef;
  9462				} else if (pf > p1) {
  9463					pf = p1;
  9464					gerr = gef;
  9465					perr = pef;
  9466				}
  9467				rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n",
  9468					   p1, pf, gef & 0x0F, pef & 0x3F);
  9469			}
  9470	
  9471		ges[ch_idx] = gerr & 0x0F;
  9472		pes[ch_idx] = perr & 0x3F;
  9473	}
  9474

diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
index f51bf27f9f7942..47d8d9e034abb4 100644
--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
@@ -9041,6 +9041,907 @@  static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev)
 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
 }
 
+static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev,
+				  struct rf_reg_pair rf_reg_record[][13], u8 chain)
+{
+	u8 rfvalue = 0;
+
+	if (chain == CHAIN_0) {
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
+		rf_reg_record[CHAIN_0][0].bank = 0;
+		rf_reg_record[CHAIN_0][0].reg = 1;
+		rf_reg_record[CHAIN_0][0].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
+		rf_reg_record[CHAIN_0][1].bank = 0;
+		rf_reg_record[CHAIN_0][1].reg = 2;
+		rf_reg_record[CHAIN_0][1].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
+		rf_reg_record[CHAIN_0][2].bank = 0;
+		rf_reg_record[CHAIN_0][2].reg = 35;
+		rf_reg_record[CHAIN_0][2].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
+		rf_reg_record[CHAIN_0][3].bank = 0;
+		rf_reg_record[CHAIN_0][3].reg = 42;
+		rf_reg_record[CHAIN_0][3].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
+		rf_reg_record[CHAIN_0][4].bank = 4;
+		rf_reg_record[CHAIN_0][4].reg = 0;
+		rf_reg_record[CHAIN_0][4].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2);
+		rf_reg_record[CHAIN_0][5].bank = 4;
+		rf_reg_record[CHAIN_0][5].reg = 2;
+		rf_reg_record[CHAIN_0][5].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34);
+		rf_reg_record[CHAIN_0][6].bank = 4;
+		rf_reg_record[CHAIN_0][6].reg = 34;
+		rf_reg_record[CHAIN_0][6].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
+		rf_reg_record[CHAIN_0][7].bank = 5;
+		rf_reg_record[CHAIN_0][7].reg = 3;
+		rf_reg_record[CHAIN_0][7].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
+		rf_reg_record[CHAIN_0][8].bank = 5;
+		rf_reg_record[CHAIN_0][8].reg = 4;
+		rf_reg_record[CHAIN_0][8].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
+		rf_reg_record[CHAIN_0][9].bank = 5;
+		rf_reg_record[CHAIN_0][9].reg = 17;
+		rf_reg_record[CHAIN_0][9].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
+		rf_reg_record[CHAIN_0][10].bank = 5;
+		rf_reg_record[CHAIN_0][10].reg = 18;
+		rf_reg_record[CHAIN_0][10].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
+		rf_reg_record[CHAIN_0][11].bank = 5;
+		rf_reg_record[CHAIN_0][11].reg = 19;
+		rf_reg_record[CHAIN_0][11].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
+		rf_reg_record[CHAIN_0][12].bank = 5;
+		rf_reg_record[CHAIN_0][12].reg = 20;
+		rf_reg_record[CHAIN_0][12].value = rfvalue;
+	} else if (chain == CHAIN_1) {
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
+		rf_reg_record[CHAIN_1][0].bank = 0;
+		rf_reg_record[CHAIN_1][0].reg = 1;
+		rf_reg_record[CHAIN_1][0].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
+		rf_reg_record[CHAIN_1][1].bank = 0;
+		rf_reg_record[CHAIN_1][1].reg = 2;
+		rf_reg_record[CHAIN_1][1].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
+		rf_reg_record[CHAIN_1][2].bank = 0;
+		rf_reg_record[CHAIN_1][2].reg = 35;
+		rf_reg_record[CHAIN_1][2].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
+		rf_reg_record[CHAIN_1][3].bank = 0;
+		rf_reg_record[CHAIN_1][3].reg = 42;
+		rf_reg_record[CHAIN_1][3].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
+		rf_reg_record[CHAIN_1][4].bank = 6;
+		rf_reg_record[CHAIN_1][4].reg = 0;
+		rf_reg_record[CHAIN_1][4].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2);
+		rf_reg_record[CHAIN_1][5].bank = 6;
+		rf_reg_record[CHAIN_1][5].reg = 2;
+		rf_reg_record[CHAIN_1][5].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34);
+		rf_reg_record[CHAIN_1][6].bank = 6;
+		rf_reg_record[CHAIN_1][6].reg = 34;
+		rf_reg_record[CHAIN_1][6].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
+		rf_reg_record[CHAIN_1][7].bank = 7;
+		rf_reg_record[CHAIN_1][7].reg = 3;
+		rf_reg_record[CHAIN_1][7].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
+		rf_reg_record[CHAIN_1][8].bank = 7;
+		rf_reg_record[CHAIN_1][8].reg = 4;
+		rf_reg_record[CHAIN_1][8].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
+		rf_reg_record[CHAIN_1][9].bank = 7;
+		rf_reg_record[CHAIN_1][9].reg = 17;
+		rf_reg_record[CHAIN_1][9].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
+		rf_reg_record[CHAIN_1][10].bank = 7;
+		rf_reg_record[CHAIN_1][10].reg = 18;
+		rf_reg_record[CHAIN_1][10].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
+		rf_reg_record[CHAIN_1][11].bank = 7;
+		rf_reg_record[CHAIN_1][11].reg = 19;
+		rf_reg_record[CHAIN_1][11].value = rfvalue;
+		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
+		rf_reg_record[CHAIN_1][12].bank = 7;
+		rf_reg_record[CHAIN_1][12].reg = 20;
+		rf_reg_record[CHAIN_1][12].value = rfvalue;
+	} else {
+		rt2x00_warn(rt2x00dev, "Unknown chain = %u\n", chain);
+	}
+}
+
+static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev,
+				    struct rf_reg_pair rf_record[][13])
+{
+	u8 chain_index = 0, record_index = 0;
+	u8 bank = 0, rf_register = 0, value = 0;
+
+	for (chain_index = 0; chain_index < 2; chain_index++) {
+		for (record_index = 0; record_index < 13; record_index++) {
+			bank = rf_record[chain_index][record_index].bank;
+			rf_register = rf_record[chain_index][record_index].reg;
+			value = rf_record[chain_index][record_index].value;
+			rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value);
+			rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n",
+				   bank, rf_register, value);
+		}
+	}
+}
+
+static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev)
+{
+	rt2800_bbp_write(rt2x00dev, 158, 0xAA);
+	rt2800_bbp_write(rt2x00dev, 159, 0x00);
+
+	rt2800_bbp_write(rt2x00dev, 158, 0xAB);
+	rt2800_bbp_write(rt2x00dev, 159, 0x0A);
+
+	rt2800_bbp_write(rt2x00dev, 158, 0xAC);
+	rt2800_bbp_write(rt2x00dev, 159, 0x3F);
+
+	rt2800_bbp_write(rt2x00dev, 158, 0xAD);
+	rt2800_bbp_write(rt2x00dev, 159, 0x3F);
+
+	rt2800_bbp_write(rt2x00dev, 244, 0x40);
+}
+
+static u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg)
+{
+	u32 macvalue = 0;
+	int fftout_i = 0, fftout_q = 0;
+	u32 ptmp = 0, pint = 0;
+	u8 bbp = 0;
+	u8 tidxi;
+
+	rt2800_bbp_write(rt2x00dev, 158, 0x00);
+	rt2800_bbp_write(rt2x00dev, 159, 0x9b);
+
+	bbp = 0x9b;
+
+	while (bbp == 0x9b) {
+		usleep_range(10, 50);
+		bbp = rt2800_bbp_read(rt2x00dev, 159);
+		bbp = bbp & 0xff;
+	}
+
+	rt2800_bbp_write(rt2x00dev, 158, 0xba);
+	rt2800_bbp_write(rt2x00dev, 159, tidx);
+	rt2800_bbp_write(rt2x00dev, 159, tidx);
+	rt2800_bbp_write(rt2x00dev, 159, tidx);
+
+	macvalue = rt2800_register_read(rt2x00dev, 0x057C);
+
+	fftout_i = (macvalue >> 16);
+	fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
+	fftout_q = (macvalue & 0xffff);
+	fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
+	ptmp = (fftout_i * fftout_i);
+	ptmp = ptmp + (fftout_q * fftout_q);
+	pint = ptmp;
+	rt2x00_dbg(rt2x00dev, "I = %d,  Q = %d, power = %x\n", fftout_i, fftout_q, pint);
+	if (read_neg) {
+		pint = pint >> 1;
+		tidxi = 0x40 - tidx;
+		tidxi = tidxi & 0x3f;
+
+		rt2800_bbp_write(rt2x00dev, 158, 0xba);
+		rt2800_bbp_write(rt2x00dev, 159, tidxi);
+		rt2800_bbp_write(rt2x00dev, 159, tidxi);
+		rt2800_bbp_write(rt2x00dev, 159, tidxi);
+
+		macvalue = rt2800_register_read(rt2x00dev, 0x057C);
+
+		fftout_i = (macvalue >> 16);
+		fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
+		fftout_q = (macvalue & 0xffff);
+		fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
+		ptmp = (fftout_i * fftout_i);
+		ptmp = ptmp + (fftout_q * fftout_q);
+		ptmp = ptmp >> 1;
+		pint = pint + ptmp;
+	}
+
+	return pint;
+}
+
+static u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx)
+{
+	u32 macvalue = 0;
+	int fftout_i = 0, fftout_q = 0;
+	u32 ptmp = 0, pint = 0;
+
+	rt2800_bbp_write(rt2x00dev, 158, 0xBA);
+	rt2800_bbp_write(rt2x00dev, 159, tidx);
+	rt2800_bbp_write(rt2x00dev, 159, tidx);
+	rt2800_bbp_write(rt2x00dev, 159, tidx);
+
+	macvalue = rt2800_register_read(rt2x00dev, 0x057C);
+
+	fftout_i = (macvalue >> 16);
+	fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
+	fftout_q = (macvalue & 0xffff);
+	fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
+	ptmp = (fftout_i * fftout_i);
+	ptmp = ptmp + (fftout_q * fftout_q);
+	pint = ptmp;
+
+	return pint;
+}
+
+static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc)
+{
+	u8 bbp = 0;
+
+	rt2800_bbp_write(rt2x00dev, 158, 0xb0);
+	bbp = alc | 0x80;
+	rt2800_bbp_write(rt2x00dev, 159, bbp);
+
+	if (ch_idx == 0)
+		bbp = (iorq == 0) ? 0xb1 : 0xb2;
+	else
+		bbp = (iorq == 0) ? 0xb8 : 0xb9;
+
+	rt2800_bbp_write(rt2x00dev, 158, bbp);
+	bbp = dc;
+	rt2800_bbp_write(rt2x00dev, 159, bbp);
+}
+
+static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx,
+			       u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2])
+{
+	u32 p0 = 0, p1 = 0, pf = 0;
+	char idx0 = 0, idx1 = 0;
+	u8 idxf[] = {0x00, 0x00};
+	u8 ibit = 0x20;
+	u8 iorq;
+	char bidx;
+
+	rt2800_bbp_write(rt2x00dev, 158, 0xb0);
+	rt2800_bbp_write(rt2x00dev, 159, 0x80);
+
+	for (bidx = 5; bidx >= 0; bidx--) {
+		for (iorq = 0; iorq <= 1; iorq++) {
+			if (idxf[iorq] == 0x20) {
+				idx0 = 0x20;
+				p0 = pf;
+			} else {
+				idx0 = idxf[iorq] - ibit;
+				idx0 = idx0 & 0x3F;
+				rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0);
+				p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
+			}
+
+			idx1 = idxf[iorq] + (bidx == 5 ? 0 : ibit);
+			idx1 = idx1 & 0x3F;
+			rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1);
+			p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
+
+			rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n",
+				   alc_idx, iorq, idxf[iorq]);
+			rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x\n",
+				   p0, p1, pf, idx0, idx1, ibit);
+
+			if (bidx != 5 && pf <= p0 && pf < p1) {
+				idxf[iorq] = idxf[iorq];
+			} else if (p0 < p1) {
+				pf = p0;
+				idxf[iorq] = idx0 & 0x3F;
+			} else {
+				pf = p1;
+				idxf[iorq] = idx1 & 0x3F;
+			}
+			rt2x00_dbg(rt2x00dev, "IorQ=%u, idx_final[%u]:%x, pf:%8x\n",
+				   iorq, iorq, idxf[iorq], pf);
+
+			rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]);
+		}
+		ibit = ibit >> 1;
+	}
+	dc_result[ch_idx][alc_idx][0] = idxf[0];
+	dc_result[ch_idx][alc_idx][1] = idxf[1];
+}
+
+static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)
+{
+	u32 p0 = 0, p1 = 0, pf = 0;
+	char perr = 0, gerr = 0, iq_err = 0;
+	char pef = 0, gef = 0;
+	char psta, pend;
+	char gsta, gend;
+
+	u8 ibit = 0x20;
+	u8 first_search = 0x00, touch_neg_max = 0x00;
+	char idx0 = 0, idx1 = 0;
+	u8 gop;
+	u8 bbp = 0;
+	char bidx;
+
+	for (bidx = 5; bidx >= 1; bidx--) {
+		for (gop = 0; gop < 2; gop++) {
+			if (gop == 1 || bidx < 4) {
+				if (gop == 0)
+					iq_err = gerr;
+				else
+					iq_err = perr;
+
+				first_search = (gop == 0) ? (bidx == 3) : (bidx == 5);
+				touch_neg_max = (gop) ? ((iq_err & 0x0F) == 0x08) :
+							((iq_err & 0x3F) == 0x20);
+
+				if (touch_neg_max) {
+					p0 = pf;
+					idx0 = iq_err;
+				} else {
+					idx0 = iq_err - ibit;
+					bbp = (ch_idx == 0) ? ((gop == 0) ? 0x28 : 0x29) :
+							      ((gop == 0) ? 0x46 : 0x47);
+
+					rt2800_bbp_write(rt2x00dev, 158, bbp);
+					rt2800_bbp_write(rt2x00dev, 159, idx0);
+
+					p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
+				}
+
+				idx1 = iq_err + (first_search ? 0 : ibit);
+				idx1 = (gop == 0) ? (idx1 & 0x0F) : (idx1 & 0x3F);
+
+				bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 :
+				      (gop == 0) ? 0x46 : 0x47;
+
+				rt2800_bbp_write(rt2x00dev, 158, bbp);
+				rt2800_bbp_write(rt2x00dev, 159, idx1);
+
+				p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
+
+				rt2x00_dbg(rt2x00dev,
+					   "p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x\n",
+					   p0, p1, pf, idx0, idx1, iq_err, gop, ibit);
+
+				if (!(!first_search && pf <= p0 && pf < p1)) {
+					if (p0 < p1) {
+						pf = p0;
+						iq_err = idx0;
+					} else {
+						pf = p1;
+						iq_err = idx1;
+					}
+				}
+
+				bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 :
+						      (gop == 0) ? 0x46 : 0x47;
+
+				rt2800_bbp_write(rt2x00dev, 158, bbp);
+				rt2800_bbp_write(rt2x00dev, 159, iq_err);
+
+				if (gop == 0)
+					gerr = iq_err;
+				else
+					perr = iq_err;
+
+				rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n",
+					   pf, gerr & 0x0F, perr & 0x3F);
+			}
+		}
+
+		if (bidx > 0)
+			ibit = (ibit >> 1);
+	}
+	gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F);
+	perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F);
+
+	gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr;
+	gsta = gerr - 1;
+	gend = gerr + 2;
+
+	perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr;
+	psta = perr - 1;
+	pend = perr + 2;
+
+	for (gef = gsta; gef <= gend; gef = gef + 1)
+		for (pef = psta; pef <= pend; pef = pef + 1) {
+			bbp = (ch_idx == 0) ? 0x28 : 0x46;
+			rt2800_bbp_write(rt2x00dev, 158, bbp);
+			rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F);
+
+			bbp = (ch_idx == 0) ? 0x29 : 0x47;
+			rt2800_bbp_write(rt2x00dev, 158, bbp);
+			rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F);
+
+			p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
+			if (gef == gsta && pef == psta) {
+				pf = p1;
+				gerr = gef;
+				perr = pef;
+			} else if (pf > p1) {
+				pf = p1;
+				gerr = gef;
+				perr = pef;
+			}
+			rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n",
+				   p1, pf, gef & 0x0F, pef & 0x3F);
+		}
+
+	ges[ch_idx] = gerr & 0x0F;
+	pes[ch_idx] = perr & 0x3F;
+}
+
+static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev)
+{
+	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21);
+	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10);
+	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
+	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b);
+	rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81);
+	rt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81);
+	rt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee);
+	rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d);
+	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d);
+	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
+	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7);
+	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2);
+	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
+}
+
+static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev)
+{
+	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22);
+	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20);
+	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
+	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b);
+	rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81);
+	rt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81);
+	rt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee);
+	rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d);
+	rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d);
+	rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80);
+	rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7);
+	rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2);
+	rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20);
+}
+
+void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
+{
+	struct rf_reg_pair rf_store[CHAIN_NUM][13];
+	u32 macorg1 = 0;
+	u32 macorg2 = 0;
+	u32 macorg3 = 0;
+	u32 macorg4 = 0;
+	u32 macorg5 = 0;
+	u32 orig528 = 0;
+	u32 orig52c = 0;
+
+	u32 savemacsysctrl = 0;
+	u32 macvalue = 0;
+	u32 mac13b8 = 0;
+	u32 p0 = 0, p1 = 0;
+	u32 p0_idx10 = 0, p1_idx10 = 0;
+
+	u8 rfvalue;
+	u8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2];
+	u8 ger[CHAIN_NUM], per[CHAIN_NUM];
+
+	u8 vga_gain[] = {14, 14};
+	u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0;
+	u8 bbpr30, rfb0r39, rfb0r42;
+	u8 bbpr1;
+	u8 bbpr4;
+	u8 bbpr241, bbpr242;
+	u8 count_step;
+
+	static const u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c};
+	static const u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30,
+					      0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F};
+	static const u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08};
+
+	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
+	macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
+	macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
+	macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
+	macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
+	macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
+	mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
+	orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
+	orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
+
+	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
+	macvalue &= (~0x04);
+	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
+
+	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
+		rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
+
+	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
+	macvalue &= (~0x08);
+	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
+
+	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
+		rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
+
+	for (ch_idx = 0; ch_idx < 2; ch_idx++)
+		rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
+
+	bbpr30 = rt2800_bbp_read(rt2x00dev, 30);
+	rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39);
+	rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
+
+	rt2800_bbp_write(rt2x00dev, 30, 0x1F);
+	rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80);
+	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B);
+
+	rt2800_bbp_write(rt2x00dev, 23, 0x00);
+	rt2800_bbp_write(rt2x00dev, 24, 0x00);
+
+	rt2800_setbbptonegenerator(rt2x00dev);
+
+	for (ch_idx = 0; ch_idx < 2; ch_idx++) {
+		rt2800_bbp_write(rt2x00dev, 23, 0x00);
+		rt2800_bbp_write(rt2x00dev, 24, 0x00);
+		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
+		rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
+		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
+		rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
+		rt2800_register_write(rt2x00dev, 0x13b8, 0x10);
+		udelay(1);
+
+		if (ch_idx == 0)
+			rt2800_rf_aux_tx0_loopback(rt2x00dev);
+		else
+			rt2800_rf_aux_tx1_loopback(rt2x00dev);
+
+		udelay(1);
+
+		if (ch_idx == 0)
+			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
+		else
+			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
+
+		rt2800_bbp_write(rt2x00dev, 158, 0x05);
+		rt2800_bbp_write(rt2x00dev, 159, 0x00);
+
+		rt2800_bbp_write(rt2x00dev, 158, 0x01);
+		if (ch_idx == 0)
+			rt2800_bbp_write(rt2x00dev, 159, 0x00);
+		else
+			rt2800_bbp_write(rt2x00dev, 159, 0x01);
+
+		vga_gain[ch_idx] = 18;
+		for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
+			rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]);
+			rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]);
+
+			macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3);
+			macvalue &= (~0x0000F1F1);
+			macvalue |= (rf_gain[rf_alc_idx] << 4);
+			macvalue |= (rf_gain[rf_alc_idx] << 12);
+			rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue);
+			macvalue = (0x0000F1F1);
+			rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue);
+
+			if (rf_alc_idx == 0) {
+				rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21);
+				for (; vga_gain[ch_idx] > 0;
+				     vga_gain[ch_idx] = vga_gain[ch_idx] - 2) {
+					rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
+					rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
+					rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
+					rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
+					rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
+					p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
+					rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21);
+					p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
+					rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1);
+					if ((p0 < 7000 * 7000) && (p1 < (7000 * 7000)))
+						break;
+				}
+
+				rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
+				rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
+
+				rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
+					   rfvga_gain_table[vga_gain[ch_idx]]);
+
+				if (vga_gain[ch_idx] < 0)
+					vga_gain[ch_idx] = 0;
+			}
+
+			rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
+
+			rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
+			rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
+
+			rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result);
+		}
+	}
+
+	for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
+		for (idx = 0; idx < 4; idx++) {
+			rt2800_bbp_write(rt2x00dev, 158, 0xB0);
+			bbp = (idx << 2) + rf_alc_idx;
+			rt2800_bbp_write(rt2x00dev, 159, bbp);
+			rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp);
+
+			rt2800_bbp_write(rt2x00dev, 158, 0xb1);
+			bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00];
+			bbp = bbp & 0x3F;
+			rt2800_bbp_write(rt2x00dev, 159, bbp);
+			rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp);
+
+			rt2800_bbp_write(rt2x00dev, 158, 0xb2);
+			bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01];
+			bbp = bbp & 0x3F;
+			rt2800_bbp_write(rt2x00dev, 159, bbp);
+			rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp);
+
+			rt2800_bbp_write(rt2x00dev, 158, 0xb8);
+			bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00];
+			bbp = bbp & 0x3F;
+			rt2800_bbp_write(rt2x00dev, 159, bbp);
+			rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp);
+
+			rt2800_bbp_write(rt2x00dev, 158, 0xb9);
+			bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01];
+			bbp = bbp & 0x3F;
+			rt2800_bbp_write(rt2x00dev, 159, bbp);
+			rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp);
+		}
+	}
+
+	rt2800_bbp_write(rt2x00dev, 23, 0x00);
+	rt2800_bbp_write(rt2x00dev, 24, 0x00);
+
+	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
+
+	rt2800_bbp_write(rt2x00dev, 158, 0x00);
+	rt2800_bbp_write(rt2x00dev, 159, 0x00);
+
+	bbp = 0x00;
+	rt2800_bbp_write(rt2x00dev, 244, 0x00);
+
+	rt2800_bbp_write(rt2x00dev, 21, 0x01);
+	udelay(1);
+	rt2800_bbp_write(rt2x00dev, 21, 0x00);
+
+	rt2800_rf_configrecover(rt2x00dev, rf_store);
+
+	rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
+	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
+	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
+	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
+	rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
+	udelay(1);
+	rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
+	rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
+	rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
+	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
+	rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528);
+	rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c);
+	rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
+
+	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
+	macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
+	macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
+	macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
+	macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
+	macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
+
+	bbpr1 = rt2800_bbp_read(rt2x00dev, 1);
+	bbpr4 = rt2800_bbp_read(rt2x00dev, 4);
+	bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
+	bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
+	mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
+
+	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
+	macvalue &= (~0x04);
+	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
+
+	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
+		rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
+
+	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
+	macvalue &= (~0x08);
+	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
+
+	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
+		rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
+
+	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
+		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101);
+		rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
+	}
+
+	rt2800_bbp_write(rt2x00dev, 23, 0x00);
+	rt2800_bbp_write(rt2x00dev, 24, 0x00);
+
+	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
+		rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18));
+		rt2800_bbp_write(rt2x00dev, 21, 0x01);
+		udelay(1);
+		rt2800_bbp_write(rt2x00dev, 21, 0x00);
+
+		rt2800_bbp_write(rt2x00dev, 241, 0x14);
+		rt2800_bbp_write(rt2x00dev, 242, 0x80);
+		rt2800_bbp_write(rt2x00dev, 244, 0x31);
+	} else {
+		rt2800_setbbptonegenerator(rt2x00dev);
+	}
+
+	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
+	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
+	udelay(1);
+
+	rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
+
+	if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
+		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000);
+		rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
+	}
+
+	rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010);
+
+	for (ch_idx = 0; ch_idx < 2; ch_idx++)
+		rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
+
+	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B);
+	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B);
+
+	rt2800_bbp_write(rt2x00dev, 158, 0x03);
+	rt2800_bbp_write(rt2x00dev, 159, 0x60);
+	rt2800_bbp_write(rt2x00dev, 158, 0xB0);
+	rt2800_bbp_write(rt2x00dev, 159, 0x80);
+
+	for (ch_idx = 0; ch_idx < 2; ch_idx++) {
+		rt2800_bbp_write(rt2x00dev, 23, 0x00);
+		rt2800_bbp_write(rt2x00dev, 24, 0x00);
+
+		if (ch_idx == 0) {
+			rt2800_bbp_write(rt2x00dev, 158, 0x01);
+			rt2800_bbp_write(rt2x00dev, 159, 0x00);
+			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
+				bbp = bbpr1 & (~0x18);
+				bbp = bbp | 0x00;
+				rt2800_bbp_write(rt2x00dev, 1, bbp);
+			}
+			rt2800_rf_aux_tx0_loopback(rt2x00dev);
+			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
+		} else {
+			rt2800_bbp_write(rt2x00dev, 158, 0x01);
+			rt2800_bbp_write(rt2x00dev, 159, 0x01);
+			if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
+				bbp = bbpr1 & (~0x18);
+				bbp = bbp | 0x08;
+				rt2800_bbp_write(rt2x00dev, 1, bbp);
+			}
+			rt2800_rf_aux_tx1_loopback(rt2x00dev);
+			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
+		}
+
+		rt2800_bbp_write(rt2x00dev, 158, 0x05);
+		rt2800_bbp_write(rt2x00dev, 159, 0x04);
+
+		bbp = (ch_idx == 0) ? 0x28 : 0x46;
+		rt2800_bbp_write(rt2x00dev, 158, bbp);
+		rt2800_bbp_write(rt2x00dev, 159, 0x00);
+
+		if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
+			rt2800_bbp_write(rt2x00dev, 23, 0x06);
+			rt2800_bbp_write(rt2x00dev, 24, 0x06);
+			count_step = 1;
+		} else {
+			rt2800_bbp_write(rt2x00dev, 23, 0x1F);
+			rt2800_bbp_write(rt2x00dev, 24, 0x1F);
+			count_step = 2;
+		}
+
+		for (; vga_gain[ch_idx] < 19; vga_gain[ch_idx] = (vga_gain[ch_idx] + count_step)) {
+			rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
+			rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
+			rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
+
+			bbp = (ch_idx == 0) ? 0x29 : 0x47;
+			rt2800_bbp_write(rt2x00dev, 158, bbp);
+			rt2800_bbp_write(rt2x00dev, 159, 0x00);
+			p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
+			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
+				p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
+
+			bbp = (ch_idx == 0) ? 0x29 : 0x47;
+			rt2800_bbp_write(rt2x00dev, 158, bbp);
+			rt2800_bbp_write(rt2x00dev, 159, 0x21);
+			p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
+			if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags))
+				p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
+
+			rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1);
+
+			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
+				rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10);
+				if ((p0_idx10 > 7000 * 7000) || (p1_idx10 > 7000 * 7000)) {
+					if (vga_gain[ch_idx] != 0)
+						vga_gain[ch_idx] = vga_gain[ch_idx] - 1;
+					break;
+				}
+			}
+
+			if ((p0 > 2500 * 2500) || (p1 > 2500 * 2500))
+				break;
+		}
+
+		if (vga_gain[ch_idx] > 18)
+			vga_gain[ch_idx] = 18;
+		rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
+			   rfvga_gain_table[vga_gain[ch_idx]]);
+
+		bbp = (ch_idx == 0) ? 0x29 : 0x47;
+		rt2800_bbp_write(rt2x00dev, 158, bbp);
+		rt2800_bbp_write(rt2x00dev, 159, 0x00);
+
+		rt2800_iq_search(rt2x00dev, ch_idx, ger, per);
+	}
+
+	rt2800_bbp_write(rt2x00dev, 23, 0x00);
+	rt2800_bbp_write(rt2x00dev, 24, 0x00);
+	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
+
+	rt2800_bbp_write(rt2x00dev, 158, 0x28);
+	bbp = ger[CHAIN_0] & 0x0F;
+	rt2800_bbp_write(rt2x00dev, 159, bbp);
+
+	rt2800_bbp_write(rt2x00dev, 158, 0x29);
+	bbp = per[CHAIN_0] & 0x3F;
+	rt2800_bbp_write(rt2x00dev, 159, bbp);
+
+	rt2800_bbp_write(rt2x00dev, 158, 0x46);
+	bbp = ger[CHAIN_1] & 0x0F;
+	rt2800_bbp_write(rt2x00dev, 159, bbp);
+
+	rt2800_bbp_write(rt2x00dev, 158, 0x47);
+	bbp = per[CHAIN_1] & 0x3F;
+	rt2800_bbp_write(rt2x00dev, 159, bbp);
+
+	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
+		rt2800_bbp_write(rt2x00dev, 1, bbpr1);
+		rt2800_bbp_write(rt2x00dev, 241, bbpr241);
+		rt2800_bbp_write(rt2x00dev, 242, bbpr242);
+	}
+	rt2800_bbp_write(rt2x00dev, 244, 0x00);
+
+	rt2800_bbp_write(rt2x00dev, 158, 0x00);
+	rt2800_bbp_write(rt2x00dev, 159, 0x00);
+	rt2800_bbp_write(rt2x00dev, 158, 0xB0);
+	rt2800_bbp_write(rt2x00dev, 159, 0x00);
+
+	rt2800_bbp_write(rt2x00dev, 30, bbpr30);
+	rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39);
+	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
+
+	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
+		rt2800_bbp_write(rt2x00dev, 4, bbpr4);
+
+	rt2800_bbp_write(rt2x00dev, 21, 0x01);
+	udelay(1);
+	rt2800_bbp_write(rt2x00dev, 21, 0x00);
+
+	rt2800_rf_configrecover(rt2x00dev, rf_store);
+
+	rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
+	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
+	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
+	rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
+	udelay(1);
+	rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
+	rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
+	rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
+	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
+	rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
+}
+
 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
 				       bool set_bw, bool is_ht40)
 {
@@ -9653,6 +10554,7 @@  static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
 	rt2800_rxdcoc_calibration(rt2x00dev);
 	rt2800_bw_filter_calibration(rt2x00dev, true);
 	rt2800_bw_filter_calibration(rt2x00dev, false);
+	rt2800_loft_iq_calibration(rt2x00dev);
 	rt2800_rxiq_calibration(rt2x00dev);
 }
 
diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
index e1761f467b9465..3cbef77b4bd306 100644
--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
@@ -17,6 +17,16 @@ 
 #define WCID_START	33
 #define WCID_END	222
 #define STA_IDS_SIZE	(WCID_END - WCID_START + 2)
+#define CHAIN_0		0x0
+#define CHAIN_1		0x1
+#define RF_ALC_NUM	6
+#define CHAIN_NUM	2
+
+struct rf_reg_pair {
+	u8 bank;
+	u8 reg;
+	u8 value;
+};
 
 /* RT2800 driver data structure */
 struct rt2800_drv_data {

[v2,10/16] rt2x00: add TX LOFT calibration for MT7620

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